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unicorn/qemu/header_gen.py

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import
2015-08-21 07:04:50 +00:00
#!/usr/bin/python
# Unicorn Emulator Engine
# By Dang Hoang Vu & Nguyen Anh Quynh
# syntax: ./header_gen.py <arm|aarch64|x86|name>
import sys
symbols = (
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'ErrorClass_lookup',
'S0',
'S1',
'X86CPURegister32_lookup',
'_DYNAMIC',
'_GLOBAL_OFFSET_TABLE_',
'__jit_debug_descriptor',
'__jit_debug_register_code',
'_edata',
'_end',
'_fini',
'_init',
import
2015-08-21 07:04:50 +00:00
'a15_l2ctlr_read',
'a64_translate_init',
'aa32_generate_debug_exceptions',
'aa64_cacheop_access',
'aa64_daif_access',
'aa64_daif_write',
'aa64_dczid_read',
'aa64_fpcr_read',
'aa64_fpcr_write',
'aa64_fpsr_read',
'aa64_fpsr_write',
'aa64_generate_debug_exceptions',
'aa64_zva_access',
'aarch64_banked_spsr_index',
'aarch64_restore_sp',
'aarch64_save_sp',
header_gen: alphabetize general symbols
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'aarch64_sync_32_to_64',
'aarch64_sync_64_to_32',
'aarch64_tb_set_jmp_target',
import
2015-08-21 07:04:50 +00:00
'accel_find',
'accel_init_machine',
'accel_type',
'access_with_adjusted_size',
'add128',
'add16_sat',
'add16_usat',
'add192',
'add8_sat',
'add8_usat',
'addFloat128Sigs',
'addFloat32Sigs',
'addFloat64Sigs',
'addFloatx80Sigs',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'add_cpreg_to_hashtable',
'add_cpreg_to_list',
import
2015-08-21 07:04:50 +00:00
'add_qemu_ldst_label',
'address_space_access_valid',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_cache_destroy',
'address_space_cache_init',
'address_space_cache_invalidate',
import
2015-08-21 07:04:50 +00:00
'address_space_destroy',
memory: Rename mem_begin/mem_commit/mem_add helpers This renames some helpers to reflect better what they do. This should cause no behavioural change. Backports commit 8629d3fcb77e9775e44d9051bad0fb5187925eae from qemu
2018-03-12 01:34:55 +00:00
'address_space_dispatch_compact',
memory: Move AddressSpaceDispatch from AddressSpace to FlatView As we are going to share FlatView's between AddressSpace's, and AddressSpaceDispatch is a structure to perform quick lookup in FlatView, this moves ASD to FlatView. After previosly open coded ASD rendering, we can also remove as->next_dispatch as the new FlatView pointer is stored on a stack and set to an AS atomically. flatview_destroy() is executed under RCU instead of address_space_dispatch_free() now. This makes mem_begin/mem_commit to work with ASD and mem_add with FV as later on mem_add will be taking FV as an argument anyway. This should cause no behavioural change. Backports commit 66a6df1dc6d5b28cc3e65db0d71683fbdddc6b62 from qemu
2018-03-12 00:33:08 +00:00
'address_space_dispatch_free',
memory: Rename mem_begin/mem_commit/mem_add helpers This renames some helpers to reflect better what they do. This should cause no behavioural change. Backports commit 8629d3fcb77e9775e44d9051bad0fb5187925eae from qemu
2018-03-12 01:34:55 +00:00
'address_space_dispatch_new',
import
2015-08-21 07:04:50 +00:00
'address_space_get_flatview',
'address_space_init',
'address_space_init_dispatch',
exec: introduce address_space_get_iotlb_entry() This patch introduces a helper to query the iotlb entry for a possible iova. This will be used by later device IOTLB API to enable the capability for a dataplane (e.g vhost) to query the IOTLB. Backports commit 052c8fa9983f553fdfa0d61034774070dd639c2b from qemu
2018-03-01 18:03:39 +00:00
'address_space_get_iotlb_entry',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_ldl',
'address_space_ldl_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_ldl_be_cached',
'address_space_ldl_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_ldl_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_ldl_le_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_ldq',
'address_space_ldq_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_ldq_be_cached',
'address_space_ldq_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_ldq_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_ldq_le_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_ldub',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_ldub_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_lduw',
'address_space_lduw_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_lduw_be_cached',
'address_space_lduw_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_lduw_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_lduw_le_cached',
import
2015-08-21 07:04:50 +00:00
'address_space_lookup_region',
'address_space_map',
'address_space_rw',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stb',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stb_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stl',
'address_space_stl_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stl_be_cached',
'address_space_stl_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stl_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stl_le_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stl_notdirty',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stl_notdirty_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stq',
'address_space_stq_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stq_be_cached',
'address_space_stq_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stq_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stq_le_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stw',
'address_space_stw_be',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stw_be_cached',
'address_space_stw_cached',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_stw_le',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'address_space_stw_le_cached',
memory: Move AddressSpaceDispatch from AddressSpace to FlatView As we are going to share FlatView's between AddressSpace's, and AddressSpaceDispatch is a structure to perform quick lookup in FlatView, this moves ASD to FlatView. After previosly open coded ASD rendering, we can also remove as->next_dispatch as the new FlatView pointer is stored on a stack and set to an AS atomically. flatview_destroy() is executed under RCU instead of address_space_dispatch_free() now. This makes mem_begin/mem_commit to work with ASD and mem_add with FV as later on mem_add will be taking FV as an argument anyway. This should cause no behavioural change. Backports commit 66a6df1dc6d5b28cc3e65db0d71683fbdddc6b62 from qemu
2018-03-12 00:33:08 +00:00
'address_space_to_dispatch',
memory: Switch memory from using AddressSpace to FlatView FlatView's will be shared between AddressSpace's and subpage_t and MemoryRegionSection cannot store AS anymore, hence this change. In particular, for: typedef struct subpage_t { MemoryRegion iomem; - AddressSpace *as; + FlatView *fv; hwaddr base; uint16_t sub_section[]; } subpage_t; struct MemoryRegionSection { MemoryRegion *mr; - AddressSpace *address_space; + FlatView *fv; hwaddr offset_within_region; Int128 size; hwaddr offset_within_address_space; bool readonly; }; This should cause no behavioural change. Backports commit 166206845f7fd75e720e6feea0bb01957c8da07f from qemu
2018-03-12 00:57:29 +00:00
'address_space_to_flatview',
import
2015-08-21 07:04:50 +00:00
'address_space_translate_for_iotlb',
'address_space_translate_internal',
'address_space_unmap',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'address_space_unregister',
import
2015-08-21 07:04:50 +00:00
'address_space_update_topology',
'address_space_update_topology_pass',
'address_space_write',
'addrrange_contains',
'addrrange_end',
'addrrange_equal',
'addrrange_intersection',
'addrrange_intersects',
'addrrange_make',
'adjust_endianness',
'all_helpers',
'alloc_code_gen_buffer',
'alloc_entry',
'always_true',
'arm1026_initfn',
'arm1136_initfn',
'arm1136_r2_initfn',
'arm1176_initfn',
'arm11mpcore_initfn',
'arm926_initfn',
'arm946_initfn',
arm: Correctly handle watchpoints for BE32 CPUs In BE32 mode, sub-word size watchpoints can fail to trigger because the address of the access is adjusted in the opcode helpers before being compared with the watchpoint registers. This patch reverses the address adjustment before performing the comparison with the help of a new CPUClass hook. This version of the patch augments and tidies up comments a little. Backports commit 40612000599e52e792d23c998377a0fa429c4036 from qemu
2018-03-02 05:24:19 +00:00
'arm_adjust_watchpoint_address',
import
2015-08-21 07:04:50 +00:00
'arm_ccnt_enabled',
'arm_cp_read_zero',
'arm_cp_reset_ignore',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_cp_write_ignore',
import
2015-08-21 07:04:50 +00:00
'arm_cpu_do_interrupt',
boards.h: Define new flag ignore_memory_transaction_failures Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Backports commit ed860129acd3fcd0b1e47884e810212aaca4d21b from qemu
2018-03-05 02:25:04 +00:00
'arm_cpu_do_transaction_failed',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_cpu_do_unaligned_access',
import
2015-08-21 07:04:50 +00:00
'arm_cpu_exec_interrupt',
'arm_cpu_finalizefn',
target-arm: Implement cpu_get_phys_page_attrs_debug Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug. Backports commit 0faea0c7e6b729c64035b3591b184eeeeef6f1d4 from qemu
2018-02-19 03:14:34 +00:00
'arm_cpu_get_phys_page_attrs_debug',
import
2015-08-21 07:04:50 +00:00
'arm_cpu_initfn',
'arm_cpu_list',
'arm_cpu_post_init',
'arm_cpu_realizefn',
'arm_cpu_register_gdb_regs_for_features',
'arm_cpu_register_types',
'arm_cpu_set_pc',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_cpus',
import
2015-08-21 07:04:50 +00:00
'arm_current_el',
'arm_dc_feature',
target-arm: Implement checking of fired watchpoint ARM stops before access to a location covered by watchpoint. Also, QEMU watchpoint fire is not necessarily an architectural watchpoint match. Unfortunately, that is hardly possible to ignore a fired watchpoint in debug exception handler. So move watchpoint check from debug exception handler to the dedicated watchpoint checking callback. Backports commit 3826121d9298cde1d29ead05910e1f40125ee9b0 from qemu
2018-02-20 16:50:26 +00:00
'arm_debug_check_watchpoint',
import
2015-08-21 07:04:50 +00:00
'arm_debug_excp_handler',
'arm_debug_target_el',
'arm_el_is_aa64',
'arm_env_get_cpu',
'arm_excp_unmasked',
'arm_feature',
target-arm: Introduce DisasCompare Split arm_gen_test_cc into 3 functions, so that it can be reused for non-branch TCG comparisons. Backports commit 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd from qemu
2018-02-11 04:42:08 +00:00
'arm_free_cc',
import
2015-08-21 07:04:50 +00:00
'arm_gen_test_cc',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_generate_debug_exceptions',
target-arm: Add the Hypervisor timer Backports commit b0e66d95e4f587b5818d2760668301ee0871ba5e from qemu
2018-02-15 01:14:33 +00:00
'arm_gt_htimer_cb',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_gt_ptimer_cb',
target-arm: Add the AArch64 view of the Secure physical timer On CPUs with EL3, there are two physical timers, one for Secure and one for Non-secure. Implement this extra timer and the AArch64 registers which access it. Backports commit b4d3978c2fdf944e428a46d2850dbd950b6fbe78 from qemu
2018-02-15 01:42:45 +00:00
'arm_gt_stimer_cb',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_gt_vtimer_cb',
import
2015-08-21 07:04:50 +00:00
'arm_handle_psci_call',
'arm_is_psci_call',
'arm_is_secure',
'arm_is_secure_below_el3',
target-arm: Introduce DisasCompare Split arm_gen_test_cc into 3 functions, so that it can be reused for non-branch TCG comparisons. Backports commit 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd from qemu
2018-02-11 04:42:08 +00:00
'arm_jump_cc',
import
2015-08-21 07:04:50 +00:00
'arm_ldl_code',
'arm_lduw_code',
'arm_log_exception',
target-arm: Update interrupt handling to use target EL Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Backports commit 012a906b19e99b126403ff4a257617dab9b34163 from qemu
2018-02-13 03:40:02 +00:00
'arm_phys_excp_target_el',
import
2015-08-21 07:04:50 +00:00
'arm_reg_read',
'arm_reg_reset',
'arm_reg_write',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_release',
import
2015-08-21 07:04:50 +00:00
'arm_rmode_to_sf',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_s1_regime_using_lpae_format',
import
2015-08-21 07:04:50 +00:00
'arm_singlestep_active',
target-arm: Introduce DisasCompare Split arm_gen_test_cc into 3 functions, so that it can be reused for non-branch TCG comparisons. Backports commit 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd from qemu
2018-02-11 04:42:08 +00:00
'arm_test_cc',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'arm_tlb_fill',
import
2015-08-21 07:04:50 +00:00
'arm_translate_init',
'arm_v7m_class_init',
'arm_v7m_cpu_do_interrupt',
'ats_access',
'ats_write',
'bad_mode_switch',
'bank_number',
'bitmap_zero_extend',
'bp_wp_matches',
'breakpoint_invalidate',
'build_page_bitmap',
'bus_add_child',
'bus_class_init',
'bus_info',
'bus_unparent',
'cache_block_ops_cp_reginfo',
'cache_dirty_status_cp_reginfo',
'cache_test_clean_cp_reginfo',
'call_recip_estimate',
'can_merge',
'capacity_increase',
'ccsidr_read',
'check_ap',
'check_breakpoints',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'check_exit_request',
import
2015-08-21 07:04:50 +00:00
'check_watchpoints',
'cho',
'clear_bit',
'clz32',
'clz64',
'cmp_flatrange_addr',
'code_gen_alloc',
'commonNaNToFloat128',
'commonNaNToFloat16',
'commonNaNToFloat32',
'commonNaNToFloat64',
'commonNaNToFloatx80',
'compute_abs_deadline',
'cond_name',
'configure_accelerator',
'container_get',
'container_info',
'container_register_types',
'contextidr_write',
'core_log_global_start',
'core_log_global_stop',
'core_memory_listener',
'cortex_a15_initfn',
'cortex_a8_initfn',
'cortex_a9_initfn',
'cortex_m3_initfn',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'cortexa15_cp_reginfo',
'cortexa8_cp_reginfo',
'cortexa9_cp_reginfo',
import
2015-08-21 07:04:50 +00:00
'countLeadingZeros32',
'countLeadingZeros64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'count_cpreg',
import
2015-08-21 07:04:50 +00:00
'cp_access_ok',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'cp_reg_reset',
'cp_reginfo',
import
2015-08-21 07:04:50 +00:00
'cpacr_write',
'cpreg_field_is_64bit',
'cpreg_key_compare',
'cpreg_make_keylist',
'cpreg_to_kvm_id',
'cpsr_read',
'cpsr_write',
'cptype_valid',
'cpu_abort',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'cpu_address_space_init',
import
2015-08-21 07:04:50 +00:00
'cpu_arm_exec',
'cpu_arm_init',
'cpu_breakpoint_insert',
'cpu_breakpoint_remove',
'cpu_breakpoint_remove_all',
'cpu_breakpoint_remove_by_ref',
'cpu_can_do_io',
'cpu_can_run',
'cpu_class_init',
'cpu_common_class_by_name',
'cpu_common_exec_interrupt',
'cpu_common_get_arch_id',
'cpu_common_get_memory_mapping',
'cpu_common_get_paging_enabled',
'cpu_common_has_work',
'cpu_common_initfn',
'cpu_common_noop',
'cpu_common_parse_features',
'cpu_common_realizefn',
'cpu_common_reset',
'cpu_dump_statistics',
'cpu_exec_init',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'cpu_exec_init_all',
tcg: Add EXCP_ATOMIC When we cannot emulate an atomic operation within a parallel context, this exception allows us to stop the world and try again in a serial context. Backports commit fdbc2b5722f6092e47181a947c90fd4bdcc1c121 from qemu Also backports parts of commit 02d57ea115b7669f588371c86484a2e8ebc369be
2018-02-27 16:12:36 +00:00
'cpu_exec_step_atomic',
import
2015-08-21 07:04:50 +00:00
'cpu_flush_icache_range',
'cpu_gen_init',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'cpu_get_address_space',
import
2015-08-21 07:04:50 +00:00
'cpu_get_clock',
'cpu_get_real_ticks',
'cpu_get_tb_cpu_state',
'cpu_handle_debug_exception',
'cpu_handle_guest_debug',
'cpu_inb',
'cpu_inl',
'cpu_interrupt',
'cpu_interrupt_handler',
'cpu_inw',
'cpu_io_recompile',
'cpu_is_stopped',
'cpu_ldl_code',
'cpu_ldub_code',
'cpu_lduw_code',
cpu-exec: Rename cpu_resume_from_signal() to cpu_loop_exit_noexc() The function cpu_resume_from_signal() is now always called with a NULL puc argument, and is rather misnamed since it is never called from a signal handler. It is essentially forcing an exit to the top level cpu loop but without raising any exception, so rename it to cpu_loop_exit_noexc() and drop the useless unused argument. Backports commit 6886b98036a8f8f5bce8b10756ce080084cef11b from qemu
2018-02-24 22:24:41 +00:00
'cpu_loop_exit',
tcg: Add EXCP_ATOMIC When we cannot emulate an atomic operation within a parallel context, this exception allows us to stop the world and try again in a serial context. Backports commit fdbc2b5722f6092e47181a947c90fd4bdcc1c121 from qemu Also backports parts of commit 02d57ea115b7669f588371c86484a2e8ebc369be
2018-02-27 16:12:36 +00:00
'cpu_loop_exit_atomic',
cpu-exec: Rename cpu_resume_from_signal() to cpu_loop_exit_noexc() The function cpu_resume_from_signal() is now always called with a NULL puc argument, and is rather misnamed since it is never called from a signal handler. It is essentially forcing an exit to the top level cpu loop but without raising any exception, so rename it to cpu_loop_exit_noexc() and drop the useless unused argument. Backports commit 6886b98036a8f8f5bce8b10756ce080084cef11b from qemu
2018-02-24 22:24:41 +00:00
'cpu_loop_exit_noexc',
'cpu_loop_exit_restore',
import
2015-08-21 07:04:50 +00:00
'cpu_memory_rw_debug',
'cpu_mmu_index',
'cpu_outb',
'cpu_outl',
'cpu_outw',
exec: invert return value of cpu_physical_memory_get_clean, rename While it is obvious that cpu_physical_memory_get_dirty returns true even if a single page is dirty, the same is not true for cpu_physical_memory_get_clean; one would expect that it returns true only if all the pages are clean, but it actually looks for even one clean page. (By contrast, the caller of that function, cpu_physical_memory_range_includes_clean, has a good name). To clarify, rename the function to cpu_physical_memory_all_dirty and return true if _all_ the pages are dirty. This is the opposite of the previous meaning, because "all are 1" is the same as "not (any is 0)", so we have to modify cpu_physical_memory_range_includes_clean as well Backports commit 72b47e79cef36ed6ffc718f10e21001d7ec2a66f from qemu
2018-02-13 14:30:20 +00:00
'cpu_physical_memory_all_dirty',
import
2015-08-21 07:04:50 +00:00
'cpu_physical_memory_clear_dirty_range',
'cpu_physical_memory_is_clean',
'cpu_physical_memory_is_io',
'cpu_physical_memory_map',
'cpu_physical_memory_range_includes_clean',
'cpu_physical_memory_reset_dirty',
'cpu_physical_memory_rw',
'cpu_physical_memory_unmap',
'cpu_physical_memory_write_rom',
'cpu_physical_memory_write_rom_internal',
'cpu_register',
'cpu_register_types',
'cpu_restore_state',
'cpu_restore_state_from_tb',
'cpu_single_step',
'cpu_tb_exec',
'cpu_to_be64',
'cpu_to_le32',
'cpu_to_le64',
'cpu_type_info',
'cpu_unassigned_access',
'cpu_watchpoint_address_matches',
'cpu_watchpoint_insert',
'cpu_watchpoint_remove',
'cpu_watchpoint_remove_all',
'cpu_watchpoint_remove_by_ref',
'crc32c_table',
'create_new_memory_mapping',
'csselr_write',
'cto32',
'ctr_el0_access',
'ctz32',
'ctz64',
'dacr_write',
'dbgbcr_write',
'dbgbvr_write',
'dbgwcr_write',
'dbgwvr_write',
'debug_cp_reginfo',
'debug_frame',
'debug_lpae_cp_reginfo',
'define_arm_cp_regs',
'define_arm_cp_regs_with_opaque',
'define_debug_regs',
'define_one_arm_cp_reg',
'define_one_arm_cp_reg_with_opaque',
'deposit32',
'deposit64',
'deregister_tm_clones',
'device_class_base_init',
'device_class_init',
'device_finalize',
'device_get_realized',
'device_initfn',
'device_post_init',
'device_reset',
'device_set_realized',
'device_type_info',
'disas_arm_insn',
'disas_coproc_insn',
'disas_dsp_insn',
'disas_iwmmxt_insn',
'disas_neon_data_insn',
'disas_neon_ls_insn',
'disas_thumb2_insn',
'disas_thumb_insn',
'disas_vfp_insn',
'disas_vfp_v8_insn',
'do_arm_semihosting',
'do_clz16',
'do_clz8',
'do_constant_folding',
'do_constant_folding_2',
'do_constant_folding_cond',
'do_constant_folding_cond2',
'do_constant_folding_cond_32',
'do_constant_folding_cond_64',
'do_constant_folding_cond_eq',
'do_fcvt_f16_to_f32',
'do_fcvt_f32_to_f16',
'do_ssat',
'do_usad',
'do_usat',
'do_v7m_exception_exit',
'dummy_c15_cp_reginfo',
'dummy_func',
'dummy_section',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'dup_const_impl',
import
2015-08-21 07:04:50 +00:00
'end_list',
target-mips: Misaligned memory accesses for MSA MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Backports commit adc370a48fd26b92188fa4848dfb088578b1936c from qemu
2018-02-13 18:15:32 +00:00
'ensure_writable_pages',
import
2015-08-21 07:04:50 +00:00
'eq128',
'error_copy',
'error_exit',
'error_get_class',
'error_get_pretty',
error: On abort, report where the error was created This is particularly useful when we abort in error_propagate(), because there the stack backtrace doesn't lead to where the error was created. Looks like this: Unexpected error in parse_block_error_action() at .../qemu/blockdev.c:322: qemu-system-x86_64: -drive if=none,werror=foo: 'foo' invalid write error action Aborted (core dumped) Note: to get this example output, I monkey-patched drive_new() to pass &error_abort to blockdev_init(). To keep the error handling boiler plate from growing even more, all error_setFOO() become macros expanding into error_setFOO_internal() with additional __FILE__, __LINE__, __func__ arguments. Not exactly pretty, but it works. The macro trickery breaks down when you take the address of an error_setFOO(). Fortunately, we do that in just one place: qemu-ga's Windows VSS provider and requester DLL wants to call error_setg_win32() through a function pointer "to avoid linking glib to the DLL". Use error_setg_win32_internal() there. The use of the function pointer is already wrapped in a macro, so the churn isn't bad. Code size increases by some 35KiB for me (0.7%). Tolerable. Could be less if we passed relative rather than absolute source file names to the compiler, or forwent reporting __func__. Backports commit 1e9b65bb1bad51735cab6c861c29b592dccabf0e from qemu
2018-02-15 16:40:27 +00:00
'error_setg_file_open_internal',
import
2015-08-21 07:04:50 +00:00
'estimateDiv128To64',
'estimateSqrt32',
'excnames',
'excp_is_internal',
'extended_addresses_enabled',
'extended_mpu_ap_bits',
'extract32',
'extract64',
'extractFloat128Exp',
'extractFloat128Frac0',
'extractFloat128Frac1',
'extractFloat128Sign',
'extractFloat16Exp',
'extractFloat16Frac',
'extractFloat16Sign',
'extractFloat32Exp',
'extractFloat32Frac',
'extractFloat32Sign',
'extractFloat64Exp',
'extractFloat64Frac',
'extractFloat64Sign',
'extractFloatx80Exp',
'extractFloatx80Frac',
'extractFloatx80Sign',
'fcse_write',
'find_better_copy',
'find_default_machine',
'find_desc_by_name',
'find_first_bit',
'find_paging_enabled_cpu',
'find_ram_block',
'find_ram_offset',
'find_string',
'find_type',
'flatrange_equal',
memory: Rename mem_begin/mem_commit/mem_add helpers This renames some helpers to reflect better what they do. This should cause no behavioural change. Backports commit 8629d3fcb77e9775e44d9051bad0fb5187925eae from qemu
2018-03-12 01:34:55 +00:00
'flatview_add_to_dispatch',
import
2015-08-21 07:04:50 +00:00
'flatview_destroy',
'flatview_init',
'flatview_insert',
'flatview_lookup',
memory: Switch memory from using AddressSpace to FlatView FlatView's will be shared between AddressSpace's and subpage_t and MemoryRegionSection cannot store AS anymore, hence this change. In particular, for: typedef struct subpage_t { MemoryRegion iomem; - AddressSpace *as; + FlatView *fv; hwaddr base; uint16_t sub_section[]; } subpage_t; struct MemoryRegionSection { MemoryRegion *mr; - AddressSpace *address_space; + FlatView *fv; hwaddr offset_within_region; Int128 size; hwaddr offset_within_address_space; bool readonly; }; This should cause no behavioural change. Backports commit 166206845f7fd75e720e6feea0bb01957c8da07f from qemu
2018-03-12 00:57:29 +00:00
'flatview_read',
'flatview_read_continue',
'flatview_read_full',
import
2015-08-21 07:04:50 +00:00
'flatview_ref',
'flatview_simplify',
memory: Move AddressSpaceDispatch from AddressSpace to FlatView As we are going to share FlatView's between AddressSpace's, and AddressSpaceDispatch is a structure to perform quick lookup in FlatView, this moves ASD to FlatView. After previosly open coded ASD rendering, we can also remove as->next_dispatch as the new FlatView pointer is stored on a stack and set to an AS atomically. flatview_destroy() is executed under RCU instead of address_space_dispatch_free() now. This makes mem_begin/mem_commit to work with ASD and mem_add with FV as later on mem_add will be taking FV as an argument anyway. This should cause no behavioural change. Backports commit 66a6df1dc6d5b28cc3e65db0d71683fbdddc6b62 from qemu
2018-03-12 00:33:08 +00:00
'flatview_to_dispatch',
memory: Switch memory from using AddressSpace to FlatView FlatView's will be shared between AddressSpace's and subpage_t and MemoryRegionSection cannot store AS anymore, hence this change. In particular, for: typedef struct subpage_t { MemoryRegion iomem; - AddressSpace *as; + FlatView *fv; hwaddr base; uint16_t sub_section[]; } subpage_t; struct MemoryRegionSection { MemoryRegion *mr; - AddressSpace *address_space; + FlatView *fv; hwaddr offset_within_region; Int128 size; hwaddr offset_within_address_space; bool readonly; }; This should cause no behavioural change. Backports commit 166206845f7fd75e720e6feea0bb01957c8da07f from qemu
2018-03-12 00:57:29 +00:00
'flatview_translate',
import
2015-08-21 07:04:50 +00:00
'flatview_unref',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'float128ToCommonNaN',
import
2015-08-21 07:04:50 +00:00
'float128_add',
'float128_compare',
'float128_compare_internal',
'float128_compare_quiet',
'float128_default_nan',
'float128_div',
'float128_eq',
'float128_eq_quiet',
'float128_is_quiet_nan',
'float128_is_signaling_nan',
'float128_le',
'float128_le_quiet',
'float128_lt',
'float128_lt_quiet',
'float128_maybe_silence_nan',
'float128_mul',
'float128_rem',
'float128_round_to_int',
'float128_scalbn',
'float128_sqrt',
'float128_sub',
'float128_to_float32',
'float128_to_float64',
'float128_to_floatx80',
'float128_to_int32',
'float128_to_int32_round_to_zero',
'float128_to_int64',
'float128_to_int64_round_to_zero',
Resolve symbol errors with softfloat
2018-03-02 14:23:44 +00:00
'float128_to_uint32_round_to_zero',
'float128_to_uint64',
'float128_to_uint64_round_to_zero',
import
2015-08-21 07:04:50 +00:00
'float128_unordered',
'float128_unordered_quiet',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'float16ToCommonNaN',
fpu/softfloat: re-factor add/sub We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 15:16:53 +00:00
'float16_add',
fpu/softfloat: re-factor compare The compare function was already expanded from a macro. I keep the macro expansion but move most of the logic into a compare_decomposed. Backports commit 0c4c90929143a530730e2879204a55a30bf63758 from qemu
2018-03-08 17:20:35 +00:00
'float16_compare',
'float16_compare_quiet',
import
2015-08-21 07:04:50 +00:00
'float16_default_nan',
fpu/softfloat: re-factor div We can now add float16_div and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Backports commit cf07323d494f4bc225e405688c2e455c3423cc40 from qemu
2018-03-08 15:24:10 +00:00
'float16_div',
import
2015-08-21 07:04:50 +00:00
'float16_is_quiet_nan',
'float16_is_signaling_nan',
fpu/softfloat: re-factor minmax Let's do the same re-factor treatment for minmax functions. I still use the MACRO trick to expand but now all the checking code is common. Backports commit 89360067071b1844bf745682e18db7dde74cdb8d from qemu
2018-03-08 17:17:28 +00:00
'float16_max',
'float16_maxnum',
'float16_maxnummag',
import
2015-08-21 07:04:50 +00:00
'float16_maybe_silence_nan',
fpu/softfloat: re-factor minmax Let's do the same re-factor treatment for minmax functions. I still use the MACRO trick to expand but now all the checking code is common. Backports commit 89360067071b1844bf745682e18db7dde74cdb8d from qemu
2018-03-08 17:17:28 +00:00
'float16_min',
'float16_minnum',
'float16_minnummag',
fpu/softfloat: re-factor mul We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Backports commit 74d707e2cc1e406068acad8e5559cd2584b1073a from qemu
2018-03-08 15:20:37 +00:00
'float16_mul',
fpu/softfloat: re-factor muladd We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Backports commit d446830a3aac33e7221e361dad3ab1e1892646cb from qemu
2018-03-08 15:55:02 +00:00
'float16_muladd',
fpu/softfloat: re-factor round_to_int We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Backports commit dbe4d53a590f5689772b683984588b3cf6df163e from qemu
2018-03-08 16:55:05 +00:00
'float16_round_to_int',
fpu/softfloat: re-factor scalbn This is one of the simpler manipulations you could make to a floating point number. Backports commit 0bfc9f195209593e91a98cf2233753f56a2e5c02 from qemu
2018-03-08 17:15:10 +00:00
'float16_scalbn',
fpu/softfloat: re-factor sqrt This is a little bit of a departure from softfloat's original approach as we skip the estimate step in favour of a straight iteration. There is a minor optimisation to avoid calculating more bits of precision than we need however this still brings a performance drop, especially for float64 operations. Backports commit c13bb2da9eedfbc5886c8048df1bc1114b285fb0 from qemu
2018-03-08 17:23:13 +00:00
'float16_sqrt',
fpu/softfloat: implement float16_squash_input_denormal This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Backports commit 210cbd4910ae9e41e0a1785b96890ea2c291b381 from qemu
2018-03-08 14:44:13 +00:00
'float16_squash_input_denormal',
fpu/softfloat: re-factor add/sub We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 15:16:53 +00:00
'float16_sub',
fpu/softfloat: re-factor float to int/uint We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Backports commit ab52f973a504f8de0c5df64631ba4caea70a7d9e from qemu
2018-03-08 17:05:05 +00:00
'float16_to_int16',
'float16_to_int16_round_to_zero',
'float16_to_int32',
'float16_to_int32_round_to_zero',
'float16_to_int64',
'float16_to_int64_round_to_zero',
import
2015-08-21 07:04:50 +00:00
'float16_to_float32',
'float16_to_float64',
fpu/softfloat: re-factor float to int/uint We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Backports commit ab52f973a504f8de0c5df64631ba4caea70a7d9e from qemu
2018-03-08 17:05:05 +00:00
'float16_to_uint16',
'float16_to_uint16_round_to_zero',
'float16_to_uint32',
'float16_to_uint32_round_to_zero',
'float16_to_uint64',
'float16_to_uint64_round_to_zero',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'float32ToCommonNaN',
import
2015-08-21 07:04:50 +00:00
'float32_abs',
'float32_add',
'float32_chs',
'float32_compare',
'float32_compare_internal',
'float32_compare_quiet',
'float32_default_nan',
'float32_div',
'float32_eq',
'float32_eq_quiet',
'float32_exp2',
'float32_exp2_coefficients',
'float32_is_any_nan',
'float32_is_infinity',
'float32_is_neg',
'float32_is_quiet_nan',
'float32_is_signaling_nan',
'float32_is_zero',
'float32_is_zero_or_denormal',
'float32_le',
'float32_le_quiet',
'float32_log2',
'float32_lt',
'float32_lt_quiet',
'float32_max',
'float32_maxnum',
'float32_maxnummag',
'float32_maybe_silence_nan',
'float32_min',
'float32_minmax',
'float32_minnum',
'float32_minnummag',
'float32_mul',
'float32_muladd',
'float32_rem',
'float32_round_to_int',
'float32_scalbn',
'float32_set_sign',
'float32_sqrt',
'float32_squash_input_denormal',
'float32_sub',
'float32_to_float128',
'float32_to_float16',
'float32_to_float64',
'float32_to_floatx80',
'float32_to_int16',
'float32_to_int16_round_to_zero',
'float32_to_int32',
'float32_to_int32_round_to_zero',
'float32_to_int64',
'float32_to_int64_round_to_zero',
'float32_to_uint16',
'float32_to_uint16_round_to_zero',
'float32_to_uint32',
'float32_to_uint32_round_to_zero',
'float32_to_uint64',
'float32_to_uint64_round_to_zero',
'float32_unordered',
'float32_unordered_quiet',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'float64ToCommonNaN',
import
2015-08-21 07:04:50 +00:00
'float64_abs',
'float64_add',
'float64_chs',
'float64_compare',
'float64_compare_internal',
'float64_compare_quiet',
'float64_default_nan',
'float64_div',
'float64_eq',
'float64_eq_quiet',
'float64_is_any_nan',
'float64_is_infinity',
'float64_is_neg',
'float64_is_quiet_nan',
'float64_is_signaling_nan',
'float64_is_zero',
'float64_le',
'float64_le_quiet',
'float64_log2',
'float64_lt',
'float64_lt_quiet',
'float64_max',
'float64_maxnum',
'float64_maxnummag',
'float64_maybe_silence_nan',
'float64_min',
'float64_minmax',
'float64_minnum',
'float64_minnummag',
'float64_mul',
'float64_muladd',
'float64_rem',
'float64_round_to_int',
'float64_scalbn',
'float64_set_sign',
'float64_sqrt',
'float64_squash_input_denormal',
'float64_sub',
'float64_to_float128',
'float64_to_float16',
'float64_to_float32',
'float64_to_floatx80',
'float64_to_int16',
'float64_to_int16_round_to_zero',
'float64_to_int32',
'float64_to_int32_round_to_zero',
'float64_to_int64',
'float64_to_int64_round_to_zero',
'float64_to_uint16',
'float64_to_uint16_round_to_zero',
'float64_to_uint32',
'float64_to_uint32_round_to_zero',
'float64_to_uint64',
'float64_to_uint64_round_to_zero',
'float64_trunc_to_int',
'float64_unordered',
'float64_unordered_quiet',
'float_raise',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'floatx80ToCommonNaN',
import
2015-08-21 07:04:50 +00:00
'floatx80_add',
'floatx80_compare',
'floatx80_compare_internal',
'floatx80_compare_quiet',
'floatx80_default_nan',
'floatx80_div',
'floatx80_eq',
'floatx80_eq_quiet',
softfloat: use floatx80_infinity in softfloat Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Backports commit 0f605c889ca3fe9744166ad4149d0dff6dacb696 from qemu
2018-03-09 06:33:15 +00:00
'floatx80_infinity',
import
2015-08-21 07:04:50 +00:00
'floatx80_is_quiet_nan',
'floatx80_is_signaling_nan',
'floatx80_le',
'floatx80_le_quiet',
'floatx80_lt',
'floatx80_lt_quiet',
'floatx80_maybe_silence_nan',
'floatx80_mul',
'floatx80_rem',
Fix building for multi-arch targets
2018-03-04 02:14:02 +00:00
'floatx80_round',
import
2015-08-21 07:04:50 +00:00
'floatx80_round_to_int',
'floatx80_scalbn',
'floatx80_sqrt',
'floatx80_sub',
'floatx80_to_float128',
'floatx80_to_float32',
'floatx80_to_float64',
'floatx80_to_int32',
'floatx80_to_int32_round_to_zero',
'floatx80_to_int64',
'floatx80_to_int64_round_to_zero',
'floatx80_unordered',
'floatx80_unordered_quiet',
'flush_icache_range',
'format_string',
'fp_decode_rm',
'frame_dummy',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'free_code_gen_buffer',
import
2015-08-21 07:04:50 +00:00
'free_range',
'fstat64',
'futex_wait',
'futex_wake',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'g_list_insert_sorted_merged',
import
2015-08-21 07:04:50 +00:00
'gen_goto_tb',
'gen_helper_access_check_cp_reg',
target-arm: Fix CPU breakpoint handling A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exception handler. Generate a call to a helper to check CPU breakpoints and raise an exception only if any breakpoint matches architecturally. Backports commit 5d98bf8f38c17a348ab6e8af196088cd4953acd0 from qemu
2018-02-16 19:54:32 +00:00
'gen_helper_check_breakpoints',
import
2015-08-21 07:04:50 +00:00
'gen_helper_clear_pstate_ss',
'gen_helper_cpsr_read',
'gen_helper_cpsr_write',
target-arm: Give CPSR setting on 32-bit exception return its own helper The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Backports commit 235ea1f5c89abf30e452539b973b0dbe43d3fe2b from qemu
2018-02-21 03:06:30 +00:00
'gen_helper_cpsr_write_eret',
import
2015-08-21 07:04:50 +00:00
'gen_helper_get_cp_reg',
'gen_helper_get_cp_reg64',
'gen_helper_get_r13_banked',
'gen_helper_get_user_reg',
'gen_helper_sel_flags',
'gen_helper_set_cp_reg',
'gen_helper_set_cp_reg64',
'gen_helper_set_neon_rmode',
'gen_helper_set_r13_banked',
'gen_helper_set_rmode',
'gen_helper_set_user_reg',
'gen_helper_vfp_get_fpscr',
'gen_helper_vfp_set_fpscr',
tcg: Remove gen_intermediate_code_pc It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Backports commit 4e5e1215156662b2b153255c49d4640d82c5568b from qemu
2018-02-16 14:59:58 +00:00
'gen_intermediate_code',
import
2015-08-21 07:04:50 +00:00
'gen_lookup_tb',
'gen_new_label',
'gen_set_label',
'gen_step_complete_exception',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'generate_memory_topology',
'generic_timer_cp_reginfo',
import
2015-08-21 07:04:50 +00:00
'get_arm_cp_reginfo',
'get_clock',
'get_clock_realtime',
'get_constraint_priority',
'get_float_exception_flags',
'get_float_rounding_mode',
'get_fpstatus_ptr',
'get_level1_table_address',
'get_mem_index',
'get_next_param_value',
'get_opt_name',
'get_opt_value',
'get_page_addr_code',
'get_param_value',
'get_phys_addr',
'get_phys_addr_lpae',
'get_phys_addr_mpu',
'get_phys_addr_v5',
'get_phys_addr_v6',
'get_system_memory',
'gt_cnt_read',
'gt_cnt_reset',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'gt_cntfrq_access',
import
2015-08-21 07:04:50 +00:00
'gt_counter_access',
'gt_ctl_write',
'gt_cval_write',
'gt_get_countervalue',
'gt_pct_access',
'gt_ptimer_access',
'gt_recalc_timer',
'gt_timer_access',
'gt_tval_read',
'gt_tval_write',
'gt_vct_access',
'gt_vtimer_access',
'guest_phys_blocks_free',
'guest_phys_blocks_init',
'handle_vcvt',
'handle_vminmaxnm',
'handle_vrint',
'handle_vsel',
'has_help_option',
tcg/i386: Add vector operations The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Backports commit 770c2fc7bb70804ae9869995fd02dadd6d7656ac from qemu
2018-03-06 21:20:28 +00:00
'have_avx1',
'have_avx2',
import
2015-08-21 07:04:50 +00:00
'have_bmi1',
'have_bmi2',
tcg/i386: Handle ctpop opcode Backports commit 993508e43e6d180e9ba9b747a9657eac69aec5bb from qemu
2018-03-01 23:48:44 +00:00
'have_popcnt',
import
2015-08-21 07:04:50 +00:00
'hcr_write',
'helper_access_check_cp_reg',
'helper_add_saturate',
'helper_add_setq',
'helper_add_usaturate',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_atomic_add_fetchb',
'helper_atomic_add_fetchb_mmu',
'helper_atomic_add_fetchl_be',
'helper_atomic_add_fetchl_be_mmu',
'helper_atomic_add_fetchl_le',
'helper_atomic_add_fetchl_le_mmu',
'helper_atomic_add_fetchq_be',
'helper_atomic_add_fetchq_be_mmu',
'helper_atomic_add_fetchq_le',
'helper_atomic_add_fetchq_le_mmu',
'helper_atomic_add_fetchw_be',
'helper_atomic_add_fetchw_be_mmu',
'helper_atomic_add_fetchw_le',
'helper_atomic_add_fetchw_le_mmu',
'helper_atomic_and_fetchb',
'helper_atomic_and_fetchb_le_mmu',
'helper_atomic_and_fetchb_mmu',
'helper_atomic_and_fetchl_be',
'helper_atomic_and_fetchl_be_mmu',
'helper_atomic_and_fetchl_le',
'helper_atomic_and_fetchl_le_mmu',
'helper_atomic_and_fetchq_be',
'helper_atomic_and_fetchq_be_mmu',
'helper_atomic_and_fetchq_le',
'helper_atomic_and_fetchq_le_mmu',
'helper_atomic_and_fetchw_be',
'helper_atomic_and_fetchw_be_mmu',
'helper_atomic_and_fetchw_le',
'helper_atomic_and_fetchw_le_mmu',
'helper_atomic_cmpxchgb',
'helper_atomic_cmpxchgb',
'helper_atomic_cmpxchgb_mmu',
'helper_atomic_cmpxchgl_be',
'helper_atomic_cmpxchgl_be_mmu',
'helper_atomic_cmpxchgl_le',
'helper_atomic_cmpxchgl_le_mmu',
tcg: Add atomic128 helpers Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing paths that use it. Backports commit 7ebee43ee3e2fcd7b5063058b7ef74bc43216733 from qemu
2018-02-28 02:20:25 +00:00
'helper_atomic_cmpxchgo_be',
'helper_atomic_cmpxchgo_be_mmu',
'helper_atomic_cmpxchgo_le',
'helper_atomic_cmpxchgo_le_mmu',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_atomic_cmpxchgq_be',
'helper_atomic_cmpxchgq_be_mmu',
'helper_atomic_cmpxchgq_le',
'helper_atomic_cmpxchgq_le_mmu',
'helper_atomic_cmpxchgw_be',
'helper_atomic_cmpxchgw_be_mmu',
'helper_atomic_cmpxchgw_le',
'helper_atomic_cmpxchgw_le_mmu',
'helper_atomic_fetch_addb',
'helper_atomic_fetch_addb_mmu',
'helper_atomic_fetch_addl_be',
'helper_atomic_fetch_addl_be_mmu',
'helper_atomic_fetch_addl_le',
'helper_atomic_fetch_addl_le_mmu',
'helper_atomic_fetch_addq_be',
'helper_atomic_fetch_addq_be_mmu',
'helper_atomic_fetch_addq_le',
'helper_atomic_fetch_addq_le_mmu',
'helper_atomic_fetch_addw_be',
'helper_atomic_fetch_addw_be_mmu',
'helper_atomic_fetch_addw_le',
'helper_atomic_fetch_addw_le_mmu',
'helper_atomic_fetch_andb',
'helper_atomic_fetch_andb_mmu',
'helper_atomic_fetch_andl_be',
'helper_atomic_fetch_andl_be_mmu',
'helper_atomic_fetch_andl_le',
'helper_atomic_fetch_andl_le_mmu',
'helper_atomic_fetch_andq_be',
'helper_atomic_fetch_andq_be_mmu',
'helper_atomic_fetch_andq_le',
'helper_atomic_fetch_andq_le_mmu',
'helper_atomic_fetch_andw_be',
'helper_atomic_fetch_andw_be_mmu',
'helper_atomic_fetch_andw_le',
'helper_atomic_fetch_andw_le_mmu',
'helper_atomic_fetch_orb',
'helper_atomic_fetch_orb_mmu',
'helper_atomic_fetch_orl_be',
'helper_atomic_fetch_orl_be_mmu',
'helper_atomic_fetch_orl_le',
'helper_atomic_fetch_orl_le_mmu',
'helper_atomic_fetch_orq_be',
'helper_atomic_fetch_orq_be_mmu',
'helper_atomic_fetch_orq_le',
'helper_atomic_fetch_orq_le_mmu',
'helper_atomic_fetch_orw_be',
'helper_atomic_fetch_orw_be_mmu',
'helper_atomic_fetch_orw_le',
'helper_atomic_fetch_orw_le_mmu',
'helper_atomic_fetch_xorb',
'helper_atomic_fetch_xorb_mmu',
'helper_atomic_fetch_xorl_be',
'helper_atomic_fetch_xorl_be_mmu',
'helper_atomic_fetch_xorl_le',
'helper_atomic_fetch_xorl_le_mmu',
'helper_atomic_fetch_xorq_be',
'helper_atomic_fetch_xorq_be_mmu',
'helper_atomic_fetch_xorq_le',
'helper_atomic_fetch_xorq_le_mmu',
'helper_atomic_fetch_xorw_be',
'helper_atomic_fetch_xorw_be_mmu',
'helper_atomic_fetch_xorw_le',
'helper_atomic_fetch_xorw_le_mmu',
tcg: Add atomic128 helpers Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing paths that use it. Backports commit 7ebee43ee3e2fcd7b5063058b7ef74bc43216733 from qemu
2018-02-28 02:20:25 +00:00
'helper_atomic_ldo_be',
'helper_atomic_ldo_be_mmu',
'helper_atomic_ldo_le',
'helper_atomic_ldo_le_mmu',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_atomic_or_fetchb',
'helper_atomic_or_fetchb_mmu',
'helper_atomic_or_fetchl_be',
'helper_atomic_or_fetchl_be_mmu',
'helper_atomic_or_fetchl_le',
'helper_atomic_or_fetchl_le_mmu',
'helper_atomic_or_fetchq_be',
'helper_atomic_or_fetchq_be_mmu',
'helper_atomic_or_fetchq_le',
'helper_atomic_or_fetchq_le_mmu',
'helper_atomic_or_fetchw_be',
'helper_atomic_or_fetchw_be_mmu',
'helper_atomic_or_fetchw_le',
'helper_atomic_or_fetchw_le_mmu',
tcg: Add atomic128 helpers Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing paths that use it. Backports commit 7ebee43ee3e2fcd7b5063058b7ef74bc43216733 from qemu
2018-02-28 02:20:25 +00:00
'helper_atomic_sto_be',
'helper_atomic_sto_be_mmu',
'helper_atomic_sto_le',
'helper_atomic_sto_le_mmu',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_atomic_xchgb',
'helper_atomic_xchgb',
'helper_atomic_xchgb_mmu',
'helper_atomic_xchgl_be',
'helper_atomic_xchgl_be_mmu',
'helper_atomic_xchgl_le',
'helper_atomic_xchgl_le_mmu',
'helper_atomic_xchgq_be',
'helper_atomic_xchgq_be_mmu',
'helper_atomic_xchgq_le',
'helper_atomic_xchgq_le_mmu',
'helper_atomic_xchgw_be',
'helper_atomic_xchgw_be_mmu',
'helper_atomic_xchgw_le',
'helper_atomic_xchgw_le_mmu',
'helper_atomic_xor_fetchb',
'helper_atomic_xor_fetchb_mmu',
'helper_atomic_xor_fetchl_be',
'helper_atomic_xor_fetchl_be_mmu',
'helper_atomic_xor_fetchl_le',
'helper_atomic_xor_fetchl_le_mmu',
'helper_atomic_xor_fetchq_be',
'helper_atomic_xor_fetchq_be_mmu',
'helper_atomic_xor_fetchq_le',
'helper_atomic_xor_fetchq_le_mmu',
'helper_atomic_xor_fetchw_be',
'helper_atomic_xor_fetchw_be_mmu',
'helper_atomic_xor_fetchw_le',
'helper_atomic_xor_fetchw_le_mmu',
import
2015-08-21 07:04:50 +00:00
'helper_be_ldl_cmmu',
'helper_be_ldq_cmmu',
'helper_be_ldq_mmu',
'helper_be_ldsl_mmu',
'helper_be_ldsw_mmu',
'helper_be_ldul_mmu',
'helper_be_lduw_mmu',
'helper_be_ldw_cmmu',
'helper_be_stl_mmu',
'helper_be_stq_mmu',
'helper_be_stw_mmu',
'helper_clear_pstate_ss',
tcg: Add helpers for clrsb The number of actual invocations does not warrent an opcode, and the backends generating it. But at least we can eliminate redundant helpers. Backports commit 086920c2c8008f125fd38781072fa25c3ad158ea from qemu
2018-03-01 23:12:18 +00:00
'helper_clrsb_i32',
'helper_clrsb_i64',
tcg: Add clz and ctz opcodes Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu
2018-03-01 20:53:35 +00:00
'helper_clz_i32',
'helper_clz_i64',
tcg: Add opcode for ctpop The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Backports commit a768e4e99247911f00c5c0267c12d4e207d5f6cc from qemu
2018-03-01 23:21:05 +00:00
'helper_ctpop_i32',
'helper_ctpop_i64',
tcg: Add clz and ctz opcodes Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu
2018-03-01 20:53:35 +00:00
'helper_ctz_i32',
'helper_ctz_i64',
import
2015-08-21 07:04:50 +00:00
'helper_cpsr_read',
'helper_cpsr_write',
target-arm: Give CPSR setting on 32-bit exception return its own helper The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Backports commit 235ea1f5c89abf30e452539b973b0dbe43d3fe2b from qemu
2018-02-21 03:06:30 +00:00
'helper_cpsr_write_eret',
import
2015-08-21 07:04:50 +00:00
'helper_crc32_arm',
'helper_crc32c',
'helper_crypto_aese',
'helper_crypto_aesmc',
'helper_crypto_sha1_3reg',
'helper_crypto_sha1h',
'helper_crypto_sha1su1',
'helper_crypto_sha256h',
'helper_crypto_sha256h2',
'helper_crypto_sha256su0',
'helper_crypto_sha256su1',
target/arm: implement SHA-512 instructions This implements emulation of the new SHA-512 instructions that have been added as an optional extensions to the ARMv8 Crypto Extensions in ARM v8.2. Backports commit 90b827d131812d7f0a8abb13dba1942a2bcee821 from qemu
2018-03-07 13:35:52 +00:00
'helper_crypto_sha512h',
'helper_crypto_sha512h2',
'helper_crypto_sha512su0',
'helper_crypto_sha512su1',
target/arm: implement SM3 instructions This implements emulation of the new SM3 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Backports commit 80d6f4c6bbb718f343a832df8dee15329cc7686c from qemu
2018-03-07 13:46:41 +00:00
'helper_crypto_sm3partw1',
'helper_crypto_sm3partw2',
'helper_crypto_sm3tt',
target/arm: implement SM4 instructions This implements emulation of the new SM4 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Backports commit b6577bcd251ca0d57ae1de149e3c706b38f21587 from qemu
2018-03-07 13:56:16 +00:00
'helper_crypto_sm4e',
'helper_crypto_sm4ekey',
import
2015-08-21 07:04:50 +00:00
'helper_dc_zva',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_div_i32',
'helper_div_i64',
'helper_divu_i32',
'helper_divu_i64',
import
2015-08-21 07:04:50 +00:00
'helper_double_saturate',
'helper_exception_internal',
'helper_exception_return',
'helper_exception_with_syndrome',
tcg: Add CONFIG_ATOMIC64 Allow qemu to build on 32-bit hosts without 64-bit atomic ops. Even if we only allow 32-bit hosts to multi-thread emulate 32-bit guests, we still need some way to handle the 32-bit guest using a 64-bit atomic operation. Do so by dropping back to single-step. Backports commit df79b996a7b21c6ea7847f7927a2e1a294b86c72 from qemu
2018-02-28 02:50:04 +00:00
'helper_exit_atomic',
import
2015-08-21 07:04:50 +00:00
'helper_get_cp_reg',
'helper_get_cp_reg64',
'helper_get_r13_banked',
'helper_get_user_reg',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_add8',
'helper_gvec_add16',
'helper_gvec_add32',
'helper_gvec_add64',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_adds8',
'helper_gvec_adds16',
'helper_gvec_adds32',
'helper_gvec_adds64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_and',
'helper_gvec_andc',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_ands',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_dup8',
'helper_gvec_dup16',
'helper_gvec_dup32',
'helper_gvec_dup64',
tcg: Add generic vector ops for comparisons Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 19:07:42 +00:00
'helper_gvec_eq8',
'helper_gvec_eq16',
'helper_gvec_eq32',
'helper_gvec_eq64',
target/arm: Decode aa64 armv8.3 fcadd Backports commit 1695cd61b08d4376c11e0658836c4f08b4fc3aa1 from qemu
2018-03-09 05:55:38 +00:00
'helper_gvec_fcaddh',
'helper_gvec_fcadds',
'helper_gvec_fcaddd',
target/arm: Decode aa64 armv8.3 fcmla Backports commit d17b7cdcf4ea3e858ceee8b86fc8544bb71561e6 from qemu Also remember to commit vec_helper.
2018-03-09 06:01:42 +00:00
'helper_gvec_fcmlad',
'helper_gvec_fcmlah',
'helper_gvec_fcmlah_idx',
'helper_gvec_fcmlas',
'helper_gvec_fcmlas_idx',
tcg: Add generic vector ops for comparisons Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 19:07:42 +00:00
'helper_gvec_le8',
'helper_gvec_le16',
'helper_gvec_le32',
'helper_gvec_le64',
'helper_gvec_leu8',
'helper_gvec_leu16',
'helper_gvec_leu32',
'helper_gvec_leu64',
'helper_gvec_lt8',
'helper_gvec_lt16',
'helper_gvec_lt32',
'helper_gvec_lt64',
'helper_gvec_ltu8',
'helper_gvec_ltu16',
'helper_gvec_ltu32',
'helper_gvec_ltu64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_mov',
tcg: Add generic vector ops for multiplication Backports commit 3774030a3e523689df24a7ed22854ce7a06b0116 from qemu
2018-03-06 19:36:48 +00:00
'helper_gvec_mul8',
'helper_gvec_mul16',
'helper_gvec_mul32',
'helper_gvec_mul64',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_muls8',
'helper_gvec_muls16',
'helper_gvec_muls32',
'helper_gvec_muls64',
tcg: Add generic vector ops for comparisons Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 19:07:42 +00:00
'helper_gvec_ne8',
'helper_gvec_ne16',
'helper_gvec_ne32',
'helper_gvec_ne64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_neg8',
'helper_gvec_neg16',
'helper_gvec_neg32',
'helper_gvec_neg64',
'helper_gvec_not',
'helper_gvec_or',
'helper_gvec_orc',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_ors',
target/arm: Decode aa64 armv8.1 three same extra
2018-03-09 05:06:19 +00:00
'helper_gvec_qrdmlah_s16',
'helper_gvec_qrdmlah_s32',
'helper_gvec_qrdmlsh_s16',
'helper_gvec_qrdmlsh_s32',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'helper_gvec_sar8i',
'helper_gvec_sar16i',
'helper_gvec_sar32i',
'helper_gvec_sar64i',
'helper_gvec_shl8i',
'helper_gvec_shl16i',
'helper_gvec_shl32i',
'helper_gvec_shl64i',
'helper_gvec_shr8i',
'helper_gvec_shr16i',
'helper_gvec_shr32i',
'helper_gvec_shr64i',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_sub8',
'helper_gvec_sub16',
'helper_gvec_sub32',
'helper_gvec_sub64',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_subs8',
'helper_gvec_subs16',
'helper_gvec_subs32',
'helper_gvec_subs64',
tcg: Add generic helpers for saturating arithmetic No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive. Backports commit f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd from qemu
2018-03-06 19:46:05 +00:00
'helper_gvec_ssadd8',
'helper_gvec_ssadd16',
'helper_gvec_ssadd32',
'helper_gvec_ssadd64',
'helper_gvec_sssub8',
'helper_gvec_sssub16',
'helper_gvec_sssub32',
'helper_gvec_sssub64',
'helper_gvec_usadd8',
'helper_gvec_usadd16',
'helper_gvec_usadd32',
'helper_gvec_usadd64',
'helper_gvec_ussub8',
'helper_gvec_ussub16',
'helper_gvec_ussub32',
'helper_gvec_ussub64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'helper_gvec_xor',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'helper_gvec_xors',
import
2015-08-21 07:04:50 +00:00
'helper_iwmmxt_addcb',
'helper_iwmmxt_addcl',
'helper_iwmmxt_addcw',
'helper_iwmmxt_addnb',
'helper_iwmmxt_addnl',
'helper_iwmmxt_addnw',
'helper_iwmmxt_addsb',
'helper_iwmmxt_addsl',
'helper_iwmmxt_addsw',
'helper_iwmmxt_addub',
'helper_iwmmxt_addul',
'helper_iwmmxt_adduw',
'helper_iwmmxt_align',
'helper_iwmmxt_avgb0',
'helper_iwmmxt_avgb1',
'helper_iwmmxt_avgw0',
'helper_iwmmxt_avgw1',
'helper_iwmmxt_bcstb',
'helper_iwmmxt_bcstl',
'helper_iwmmxt_bcstw',
'helper_iwmmxt_cmpeqb',
'helper_iwmmxt_cmpeql',
'helper_iwmmxt_cmpeqw',
'helper_iwmmxt_cmpgtsb',
'helper_iwmmxt_cmpgtsl',
'helper_iwmmxt_cmpgtsw',
'helper_iwmmxt_cmpgtub',
'helper_iwmmxt_cmpgtul',
'helper_iwmmxt_cmpgtuw',
'helper_iwmmxt_insr',
'helper_iwmmxt_macsw',
'helper_iwmmxt_macuw',
'helper_iwmmxt_maddsq',
'helper_iwmmxt_madduq',
'helper_iwmmxt_maxsb',
'helper_iwmmxt_maxsl',
'helper_iwmmxt_maxsw',
'helper_iwmmxt_maxub',
'helper_iwmmxt_maxul',
'helper_iwmmxt_maxuw',
'helper_iwmmxt_minsb',
'helper_iwmmxt_minsl',
'helper_iwmmxt_minsw',
'helper_iwmmxt_minub',
'helper_iwmmxt_minul',
'helper_iwmmxt_minuw',
'helper_iwmmxt_msbb',
'helper_iwmmxt_msbl',
'helper_iwmmxt_msbw',
'helper_iwmmxt_muladdsl',
'helper_iwmmxt_muladdsw',
'helper_iwmmxt_muladdswl',
'helper_iwmmxt_mulshw',
'helper_iwmmxt_mulslw',
'helper_iwmmxt_muluhw',
'helper_iwmmxt_mululw',
'helper_iwmmxt_packsl',
'helper_iwmmxt_packsq',
'helper_iwmmxt_packsw',
'helper_iwmmxt_packul',
'helper_iwmmxt_packuq',
'helper_iwmmxt_packuw',
'helper_iwmmxt_rorl',
'helper_iwmmxt_rorq',
'helper_iwmmxt_rorw',
'helper_iwmmxt_sadb',
'helper_iwmmxt_sadw',
'helper_iwmmxt_setpsr_nz',
'helper_iwmmxt_shufh',
'helper_iwmmxt_slll',
'helper_iwmmxt_sllq',
'helper_iwmmxt_sllw',
'helper_iwmmxt_sral',
'helper_iwmmxt_sraq',
'helper_iwmmxt_sraw',
'helper_iwmmxt_srll',
'helper_iwmmxt_srlq',
'helper_iwmmxt_srlw',
'helper_iwmmxt_subnb',
'helper_iwmmxt_subnl',
'helper_iwmmxt_subnw',
'helper_iwmmxt_subsb',
'helper_iwmmxt_subsl',
'helper_iwmmxt_subsw',
'helper_iwmmxt_subub',
'helper_iwmmxt_subul',
'helper_iwmmxt_subuw',
'helper_iwmmxt_unpackhb',
'helper_iwmmxt_unpackhl',
'helper_iwmmxt_unpackhsb',
'helper_iwmmxt_unpackhsl',
'helper_iwmmxt_unpackhsw',
'helper_iwmmxt_unpackhub',
'helper_iwmmxt_unpackhul',
'helper_iwmmxt_unpackhuw',
'helper_iwmmxt_unpackhw',
'helper_iwmmxt_unpacklb',
'helper_iwmmxt_unpackll',
'helper_iwmmxt_unpacklsb',
'helper_iwmmxt_unpacklsl',
'helper_iwmmxt_unpacklsw',
'helper_iwmmxt_unpacklub',
'helper_iwmmxt_unpacklul',
'helper_iwmmxt_unpackluw',
'helper_iwmmxt_unpacklw',
'helper_ldb_cmmu',
'helper_ldb_mmu',
'helper_ldl_cmmu',
'helper_ldl_mmu',
'helper_ldq_cmmu',
'helper_ldq_mmu',
'helper_ldw_cmmu',
'helper_ldw_mmu',
'helper_le_ldl_cmmu',
'helper_le_ldq_cmmu',
'helper_le_ldq_mmu',
'helper_le_ldsl_mmu',
'helper_le_ldsw_mmu',
'helper_le_ldul_mmu',
'helper_le_lduw_mmu',
'helper_le_ldw_cmmu',
'helper_le_stl_mmu',
'helper_le_stq_mmu',
'helper_le_stw_mmu',
tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptr Instead of exporting goto_ptr directly to TCG frontends, export tcg_gen_lookup_and_goto_ptr(), which calls goto_ptr with the pointer returned by the lookup_tb_ptr() helper. This is the only use case we have for goto_ptr and lookup_tb_ptr, so having this function is very convenient. Furthermore, it trivially allows us to avoid calling the lookup helper if goto_ptr is not implemented by the backend. Backports commit cedbcb01529cb6cf9a2289cdbebbc63f6149fc18 from qemu
2018-03-03 01:56:29 +00:00
'helper_lookup_tb_ptr',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_mulsh_i32',
'helper_mulsh_i64',
'helper_muluh_i32',
'helper_muluh_i64',
target-arm: Implement MRS (banked) and MSR (banked) instructions Starting with the ARMv7 Virtualization Extensions, the A32 and T32 instruction sets provide instructions "MSR (banked)" and "MRS (banked)" which can be used to access registers for a mode other than the current one: * R<m>_<mode> * ELR_hyp * SPSR_<mode> Implement the missing instructions. Backports commit 8bfd0550be821cf27d71444e2af350de3c3d2ee3 from qemu
2018-02-22 02:43:19 +00:00
'helper_mrs_banked',
target-mips: Misaligned memory accesses for MSA MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Backports commit adc370a48fd26b92188fa4848dfb088578b1936c from qemu
2018-02-13 18:15:32 +00:00
'helper_msa_ld_b',
'helper_msa_ld_d',
'helper_msa_ld_h',
'helper_msa_ld_w',
'helper_msa_st_b',
'helper_msa_st_d',
'helper_msa_st_h',
'helper_msa_st_w',
target-arm: Implement MRS (banked) and MSR (banked) instructions Starting with the ARMv7 Virtualization Extensions, the A32 and T32 instruction sets provide instructions "MSR (banked)" and "MRS (banked)" which can be used to access registers for a mode other than the current one: * R<m>_<mode> * ELR_hyp * SPSR_<mode> Implement the missing instructions. Backports commit 8bfd0550be821cf27d71444e2af350de3c3d2ee3 from qemu
2018-02-22 02:43:19 +00:00
'helper_msr_banked',
import
2015-08-21 07:04:50 +00:00
'helper_msr_i_pstate',
'helper_neon_abd_f32',
'helper_neon_abd_s16',
'helper_neon_abd_s32',
'helper_neon_abd_s8',
'helper_neon_abd_u16',
'helper_neon_abd_u32',
'helper_neon_abd_u8',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_neon_abdl_s16',
'helper_neon_abdl_s32',
'helper_neon_abdl_s64',
'helper_neon_abdl_u16',
'helper_neon_abdl_u32',
'helper_neon_abdl_u64',
import
2015-08-21 07:04:50 +00:00
'helper_neon_abs_s16',
'helper_neon_abs_s8',
'helper_neon_acge_f32',
'helper_neon_acge_f64',
'helper_neon_acgt_f32',
'helper_neon_acgt_f64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_neon_add_u16',
'helper_neon_add_u8',
import
2015-08-21 07:04:50 +00:00
'helper_neon_addl_saturate_s32',
'helper_neon_addl_saturate_s64',
'helper_neon_addl_u16',
'helper_neon_addl_u32',
'helper_neon_ceq_f32',
'helper_neon_ceq_u16',
'helper_neon_ceq_u32',
'helper_neon_ceq_u8',
'helper_neon_cge_f32',
'helper_neon_cge_s16',
'helper_neon_cge_s32',
'helper_neon_cge_s8',
'helper_neon_cge_u16',
'helper_neon_cge_u32',
'helper_neon_cge_u8',
'helper_neon_cgt_f32',
'helper_neon_cgt_s16',
'helper_neon_cgt_s32',
'helper_neon_cgt_s8',
'helper_neon_cgt_u16',
'helper_neon_cgt_u32',
'helper_neon_cgt_u8',
'helper_neon_cls_s16',
'helper_neon_cls_s32',
'helper_neon_cls_s8',
'helper_neon_clz_u16',
'helper_neon_clz_u8',
'helper_neon_cnt_u8',
'helper_neon_fcvt_f16_to_f32',
'helper_neon_fcvt_f32_to_f16',
'helper_neon_hadd_s16',
'helper_neon_hadd_s32',
'helper_neon_hadd_s8',
'helper_neon_hadd_u16',
'helper_neon_hadd_u32',
'helper_neon_hadd_u8',
'helper_neon_hsub_s16',
'helper_neon_hsub_s32',
'helper_neon_hsub_s8',
'helper_neon_hsub_u16',
'helper_neon_hsub_u32',
'helper_neon_hsub_u8',
'helper_neon_max_s16',
'helper_neon_max_s32',
'helper_neon_max_s8',
'helper_neon_max_u16',
'helper_neon_max_u32',
'helper_neon_max_u8',
'helper_neon_min_s16',
'helper_neon_min_s32',
'helper_neon_min_s8',
'helper_neon_min_u16',
'helper_neon_min_u32',
'helper_neon_min_u8',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_neon_mul_p8',
'helper_neon_mul_u16',
'helper_neon_mul_u8',
import
2015-08-21 07:04:50 +00:00
'helper_neon_mull_p8',
'helper_neon_mull_s16',
'helper_neon_mull_s8',
'helper_neon_mull_u16',
'helper_neon_mull_u8',
'helper_neon_narrow_high_u16',
'helper_neon_narrow_high_u8',
'helper_neon_narrow_round_high_u16',
'helper_neon_narrow_round_high_u8',
'helper_neon_narrow_sat_s16',
'helper_neon_narrow_sat_s32',
'helper_neon_narrow_sat_s8',
'helper_neon_narrow_sat_u16',
'helper_neon_narrow_sat_u32',
'helper_neon_narrow_sat_u8',
'helper_neon_narrow_u16',
'helper_neon_narrow_u8',
'helper_neon_negl_u16',
'helper_neon_negl_u32',
'helper_neon_padd_u16',
'helper_neon_padd_u8',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_neon_paddl_u16',
'helper_neon_paddl_u32',
import
2015-08-21 07:04:50 +00:00
'helper_neon_pmax_s16',
'helper_neon_pmax_s8',
'helper_neon_pmax_u16',
'helper_neon_pmax_u8',
'helper_neon_pmin_s16',
'helper_neon_pmin_s8',
'helper_neon_pmin_u16',
'helper_neon_pmin_u8',
'helper_neon_pmull_64_hi',
'helper_neon_pmull_64_lo',
'helper_neon_qabs_s16',
'helper_neon_qabs_s32',
'helper_neon_qabs_s64',
'helper_neon_qabs_s8',
'helper_neon_qadd_s16',
'helper_neon_qadd_s32',
'helper_neon_qadd_s64',
'helper_neon_qadd_s8',
'helper_neon_qadd_u16',
'helper_neon_qadd_u32',
'helper_neon_qadd_u64',
'helper_neon_qadd_u8',
'helper_neon_qdmulh_s16',
'helper_neon_qdmulh_s32',
'helper_neon_qneg_s16',
'helper_neon_qneg_s32',
'helper_neon_qneg_s64',
'helper_neon_qneg_s8',
target/arm: Decode aa64 armv8.1 scalar three same extra Backports commit d9061ec3d27eb940402a7eafee3fb77ce1146ad4 from qemu
2018-03-09 04:57:21 +00:00
'helper_neon_qrdmlah_s16',
'helper_neon_qrdmlah_s32',
'helper_neon_qrdmlsh_s16',
'helper_neon_qrdmlsh_s32',
import
2015-08-21 07:04:50 +00:00
'helper_neon_qrdmulh_s16',
'helper_neon_qrdmulh_s32',
'helper_neon_qrshl_s16',
'helper_neon_qrshl_s32',
'helper_neon_qrshl_s64',
'helper_neon_qrshl_s8',
'helper_neon_qrshl_u16',
'helper_neon_qrshl_u32',
'helper_neon_qrshl_u64',
'helper_neon_qrshl_u8',
'helper_neon_qshl_s16',
'helper_neon_qshl_s32',
'helper_neon_qshl_s64',
'helper_neon_qshl_s8',
'helper_neon_qshl_u16',
'helper_neon_qshl_u32',
'helper_neon_qshl_u64',
'helper_neon_qshl_u8',
'helper_neon_qshlu_s16',
'helper_neon_qshlu_s32',
'helper_neon_qshlu_s64',
'helper_neon_qshlu_s8',
'helper_neon_qsub_s16',
'helper_neon_qsub_s32',
'helper_neon_qsub_s64',
'helper_neon_qsub_s8',
'helper_neon_qsub_u16',
'helper_neon_qsub_u32',
'helper_neon_qsub_u64',
'helper_neon_qsub_u8',
'helper_neon_qunzip16',
'helper_neon_qunzip32',
'helper_neon_qunzip8',
'helper_neon_qzip16',
'helper_neon_qzip32',
'helper_neon_qzip8',
'helper_neon_rbit_u8',
'helper_neon_rhadd_s16',
'helper_neon_rhadd_s32',
'helper_neon_rhadd_s8',
'helper_neon_rhadd_u16',
'helper_neon_rhadd_u32',
'helper_neon_rhadd_u8',
'helper_neon_rshl_s16',
'helper_neon_rshl_s32',
'helper_neon_rshl_s64',
'helper_neon_rshl_s8',
'helper_neon_rshl_u16',
'helper_neon_rshl_u32',
'helper_neon_rshl_u64',
'helper_neon_rshl_u8',
'helper_neon_shl_s16',
'helper_neon_shl_s32',
'helper_neon_shl_s64',
'helper_neon_shl_s8',
'helper_neon_shl_u16',
'helper_neon_shl_u32',
'helper_neon_shl_u64',
'helper_neon_shl_u8',
'helper_neon_sqadd_u16',
'helper_neon_sqadd_u32',
'helper_neon_sqadd_u64',
'helper_neon_sqadd_u8',
'helper_neon_sub_u16',
'helper_neon_sub_u8',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_neon_subl_u16',
'helper_neon_subl_u32',
import
2015-08-21 07:04:50 +00:00
'helper_neon_tbl',
'helper_neon_tst_u16',
'helper_neon_tst_u32',
'helper_neon_tst_u8',
'helper_neon_unarrow_sat16',
'helper_neon_unarrow_sat32',
'helper_neon_unarrow_sat8',
'helper_neon_unzip16',
'helper_neon_unzip8',
'helper_neon_uqadd_s16',
'helper_neon_uqadd_s32',
'helper_neon_uqadd_s64',
'helper_neon_uqadd_s8',
'helper_neon_widen_s16',
'helper_neon_widen_s8',
'helper_neon_widen_u16',
'helper_neon_widen_u8',
'helper_neon_zip16',
'helper_neon_zip8',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_power_down',
import
2015-08-21 07:04:50 +00:00
'helper_pre_hvc',
'helper_pre_smc',
'helper_qadd16',
'helper_qadd8',
'helper_qaddsubx',
'helper_qsub16',
'helper_qsub8',
'helper_qsubaddx',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_raise_exception',
import
2015-08-21 07:04:50 +00:00
'helper_rbit',
arm/helper.c: re-factor recpe and add recepe_f16 It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Backports commit 5eb70735af1c0b607bf2671a53aff3710cc1672f from qemu
2018-03-08 23:57:00 +00:00
'helper_recpe_f16',
import
2015-08-21 07:04:50 +00:00
'helper_recpe_f32',
'helper_recpe_f64',
'helper_recpe_u32',
'helper_recps_f32',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_rem_i32',
'helper_rem_i64',
'helper_remu_i32',
'helper_remu_i64',
import
2015-08-21 07:04:50 +00:00
'helper_ret_ldb_cmmu',
'helper_ret_ldsb_mmu',
'helper_ret_ldub_mmu',
'helper_ret_stb_mmu',
'helper_rintd',
'helper_rintd_exact',
'helper_rints',
'helper_rints_exact',
'helper_ror_cc',
arm/helper.c: re-factor rsqrte and add rsqrte_f16 Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Backports commit d719cbc7641991d16b891ffbbfc3a16a04e37b9a from qemu Also removes a load of symbols that seem unnecessary from the header_gen script
2018-03-09 03:04:58 +00:00
'helper_rsqrte_f16',
import
2015-08-21 07:04:50 +00:00
'helper_rsqrte_f32',
'helper_rsqrte_f64',
'helper_rsqrte_u32',
'helper_rsqrts_f32',
'helper_sadd16',
'helper_sadd8',
'helper_saddsubx',
'helper_sar_cc',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_sar_i32',
'helper_sar_i64',
import
2015-08-21 07:04:50 +00:00
'helper_sdiv',
'helper_sel_flags',
'helper_set_cp_reg',
'helper_set_cp_reg64',
'helper_set_neon_rmode',
'helper_set_r13_banked',
'helper_set_rmode',
'helper_set_user_reg',
target-arm: implement setend Since this is not a high-performance path, just use a helper to flip the E bit and force a lookup in the hash table since the flags have changed. Backports commit 9886ecdf31165de2d4b8bccc1a220bd6ac8bc192 from qemu
2018-02-21 07:38:42 +00:00
'helper_setend',
import
2015-08-21 07:04:50 +00:00
'helper_shadd16',
'helper_shadd8',
'helper_shaddsubx',
'helper_shl_cc',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_shl_i64',
import
2015-08-21 07:04:50 +00:00
'helper_shr_cc',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'helper_shr_i32',
'helper_shr_i64',
import
2015-08-21 07:04:50 +00:00
'helper_shsub16',
'helper_shsub8',
'helper_shsubaddx',
'helper_ssat',
'helper_ssat16',
'helper_ssub16',
'helper_ssub8',
'helper_ssubaddx',
'helper_stb_mmu',
'helper_stl_mmu',
'helper_stq_mmu',
'helper_stw_mmu',
'helper_sub_saturate',
'helper_sub_usaturate',
'helper_sxtb16',
'helper_uadd16',
'helper_uadd8',
'helper_uaddsubx',
'helper_udiv',
'helper_uhadd16',
'helper_uhadd8',
'helper_uhaddsubx',
'helper_uhsub16',
'helper_uhsub8',
'helper_uhsubaddx',
'helper_uqadd16',
'helper_uqadd8',
'helper_uqaddsubx',
'helper_uqsub16',
'helper_uqsub8',
'helper_uqsubaddx',
'helper_usad8',
'helper_usat',
'helper_usat16',
'helper_usub16',
'helper_usub8',
'helper_usubaddx',
'helper_uxtb16',
target/arm: Implement BLXNS Implement the BLXNS instruction, which allows secure code to call non-secure code. Backports commit 3e3fa230e3b8ffe119f14ba57a6bc677a411be57 from qemu
2018-03-05 08:29:41 +00:00
'helper_v7m_blxns',
target/arm: Implement BXNS, and banked stack pointers Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Backports commit fb602cb726b3ebdd01ef3b1732d74baf9fee7ec9 from qemu
2018-03-05 02:18:56 +00:00
'helper_v7m_bxns',
import
2015-08-21 07:04:50 +00:00
'helper_v7m_mrs',
'helper_v7m_msr',
target/arm: Implement TT instruction Implement the TT instruction which queries the security state and access permissions of a memory location. Backports commit 5158de241b0fb344a6c948dfcbc4e611ab5fafbe from qemu
2018-03-05 18:28:43 +00:00
'helper_v7m_tt',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_absd',
'helper_vfp_abss',
'helper_vfp_addd',
'helper_vfp_adds',
'helper_vfp_cmpd',
'helper_vfp_cmped',
'helper_vfp_cmpes',
'helper_vfp_cmps',
'helper_vfp_divd',
'helper_vfp_divs',
'helper_vfp_fcvt_f16_to_f32',
'helper_vfp_fcvt_f16_to_f64',
'helper_vfp_fcvt_f32_to_f16',
'helper_vfp_fcvt_f64_to_f16',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_vfp_fcvtds',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_fcvtsd',
'helper_vfp_get_fpscr',
'helper_vfp_maxd',
'helper_vfp_maxnumd',
'helper_vfp_maxnums',
'helper_vfp_maxs',
'helper_vfp_mind',
'helper_vfp_minnumd',
'helper_vfp_minnums',
'helper_vfp_mins',
'helper_vfp_muladdd',
'helper_vfp_muladds',
'helper_vfp_muld',
'helper_vfp_muls',
'helper_vfp_negd',
'helper_vfp_negs',
'helper_vfp_set_fpscr',
'helper_vfp_shtod',
'helper_vfp_shtos',
'helper_vfp_sitod',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_sitoh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_sitos',
'helper_vfp_sltod',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_sltoh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_sltos',
'helper_vfp_sqrtd',
'helper_vfp_sqrts',
'helper_vfp_sqtod',
'helper_vfp_sqtos',
'helper_vfp_subd',
'helper_vfp_subs',
'helper_vfp_toshd',
'helper_vfp_toshd_round_to_zero',
'helper_vfp_toshs',
'helper_vfp_toshs_round_to_zero',
'helper_vfp_tosid',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_tosih',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_tosis',
'helper_vfp_tosizd',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_tosizh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_tosizs',
'helper_vfp_tosld',
'helper_vfp_tosld_round_to_zero',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_toslh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_tosls',
'helper_vfp_tosls_round_to_zero',
'helper_vfp_tosqd',
'helper_vfp_tosqs',
'helper_vfp_touhd',
'helper_vfp_touhd_round_to_zero',
'helper_vfp_touhs',
'helper_vfp_touhs_round_to_zero',
'helper_vfp_touid',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_touih',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_touis',
'helper_vfp_touizd',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_touizh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_touizs',
'helper_vfp_tould',
'helper_vfp_tould_round_to_zero',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_toulh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_touls',
'helper_vfp_touls_round_to_zero',
'helper_vfp_touqd',
'helper_vfp_touqs',
'helper_vfp_uhtod',
'helper_vfp_uhtos',
'helper_vfp_uitod',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_uitoh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_uitos',
'helper_vfp_ultod',
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
2018-03-08 23:35:47 +00:00
'helper_vfp_ultoh',
import
2015-08-21 07:04:50 +00:00
'helper_vfp_ultos',
'helper_vfp_uqtod',
'helper_vfp_uqtos',
'helper_wfe',
'helper_wfi',
target-arm: Split DISAS_YIELD from DISAS_WFE Currently we use DISAS_WFE for both WFE and YIELD instructions. This is functionally correct because at the moment both of them are implemented as "yield this CPU back to the top level loop so another CPU has a chance to run". However it's rather confusing that YIELD ends up calling HELPER(wfe), and if we ever want to implement real behaviour for WFE and SEV it's likely to trip us up. Split out the yield codepath to use DISAS_YIELD and a new HELPER(yield) function, and have HELPER(wfe) call HELPER(yield). Backports commit 049e24a191c212d9468db84169197887f2c91586 from qemu
2018-02-14 03:46:56 +00:00
'helper_yield',
import
2015-08-21 07:04:50 +00:00
'hex2decimal',
'hw_breakpoint_update',
'hw_breakpoint_update_all',
'hw_watchpoint_update',
'hw_watchpoint_update_all',
'init_cpreg_list',
'init_lists',
'input_type_enum',
'int128_2_64',
'int128_add',
'int128_addto',
'int128_and',
'int128_eq',
'int128_ge',
'int128_get64',
'int128_gt',
'int128_le',
'int128_lt',
'int128_make64',
'int128_max',
'int128_min',
'int128_ne',
'int128_neg',
'int128_nz',
'int128_rshift',
'int128_sub',
'int128_subfrom',
'int128_zero',
fpu/softfloat: re-factor float to int/uint We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Backports commit ab52f973a504f8de0c5df64631ba4caea70a7d9e from qemu
2018-03-08 17:05:05 +00:00
'int16_to_float16',
import
2015-08-21 07:04:50 +00:00
'int16_to_float32',
'int16_to_float64',
'int32_to_float128',
fpu/softfloat: re-factor int/uint to float These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 17:10:00 +00:00
'int32_to_float16',
import
2015-08-21 07:04:50 +00:00
'int32_to_float32',
'int32_to_float64',
'int32_to_floatx80',
'int64_to_float128',
fpu/softfloat: re-factor int/uint to float These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 17:10:00 +00:00
'int64_to_float16',
import
2015-08-21 07:04:50 +00:00
'int64_to_float32',
'int64_to_float64',
'int64_to_floatx80',
'invalidate_and_set_dirty',
'invalidate_page_bitmap',
'io_readb',
'io_readl',
'io_readq',
'io_readw',
'io_writeb',
'io_writel',
'io_writeq',
'io_writew',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'iotlb_to_region',
import
2015-08-21 07:04:50 +00:00
'is_a64',
'is_help_option',
'is_valid_option_list',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'isr_read',
import
2015-08-21 07:04:50 +00:00
'iwmmxt_load_creg',
'iwmmxt_load_reg',
'iwmmxt_store_creg',
'iwmmxt_store_reg',
'kvm_to_cpreg_id',
'last_ram_offset',
'ldl_be_p',
'ldl_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldl_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldl_he_p',
'ldl_le_p',
'ldl_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldl_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldl_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldl_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldl_phys_internal',
'ldq_be_p',
'ldq_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldq_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldq_he_p',
'ldq_le_p',
'ldq_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldq_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldq_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldq_phys_cached',
import
2015-08-21 07:04:50 +00:00
'ldq_phys_internal',
'ldst_name',
'ldub_p',
'ldub_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'ldub_phys_cached',
import
2015-08-21 07:04:50 +00:00
'lduw_be_p',
'lduw_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'lduw_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'lduw_he_p',
'lduw_le_p',
'lduw_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'lduw_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'lduw_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'lduw_phys_cached',
import
2015-08-21 07:04:50 +00:00
'lduw_phys_internal',
'le128',
'linked_bp_matches',
'listener_add_address_space',
'load_cpu_offset',
'load_reg',
'load_reg_var',
'log_cpu_state',
'lpae_cp_reginfo',
'lt128',
'machine_class_init',
'machine_finalize',
'machine_info',
'machine_initfn',
'machine_register_types',
'machvirt_init',
'machvirt_machine_init',
'maj',
'mapping_conflict',
'mapping_contiguous',
'mapping_have_same_region',
'mapping_merge',
'memory_access_size',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_free',
import
2015-08-21 07:04:50 +00:00
'memory_init',
'memory_listener_match',
'memory_listener_register',
'memory_listener_unregister',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_map',
import
2015-08-21 07:04:50 +00:00
'memory_map_init',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_map_ptr',
import
2015-08-21 07:04:50 +00:00
'memory_mapping_filter',
'memory_mapping_list_add_mapping_sorted',
'memory_mapping_list_add_merge_sorted',
'memory_mapping_list_free',
'memory_mapping_list_init',
'memory_region_access_valid',
'memory_region_add_subregion',
'memory_region_add_subregion_common',
'memory_region_add_subregion_overlap',
'memory_region_big_endian',
memory: Add global-locking property to memory regions This introduces the memory region property "global_locking". It is true by default. By setting it to false, a device model can request BQL-free dispatching of region accesses to its r/w handlers. The actual BQL break-up will be provided in a separate patch. Backports commit 196ea13104f802c508e57180b2a0d2b3418989a3 from qemu
2018-02-14 13:36:25 +00:00
'memory_region_clear_global_locking',
import
2015-08-21 07:04:50 +00:00
'memory_region_clear_pending',
'memory_region_del_subregion',
'memory_region_destructor_alias',
'memory_region_destructor_none',
'memory_region_destructor_ram',
'memory_region_destructor_ram_from_ptr',
'memory_region_dispatch_read',
'memory_region_dispatch_read1',
'memory_region_dispatch_write',
'memory_region_escape_name',
'memory_region_finalize',
'memory_region_find',
memory: split memory_region_from_host from qemu_ram_addr_from_host Move the old qemu_ram_addr_from_host to memory_region_from_host and make it return an offset within the region. For qemu_ram_addr_from_host return the ram_addr_t directly, similar to what it was before commit 1b5ec23 ("memory: return MemoryRegion from qemu_ram_addr_from_host", 2013-07-04). Backports commit 07bdaa4196b51bc7ffa7c3f74e9e4a9dc8a7966a from qemu
2018-02-24 20:52:04 +00:00
'memory_region_from_host',
import
2015-08-21 07:04:50 +00:00
'memory_region_get_addr',
'memory_region_get_alignment',
'memory_region_get_container',
memory: differentiate memory_region_is_logging and memory_region_get_dirty_log_mask For now memory regions only track DIRTY_MEMORY_VGA individually, but this will change soon. To support this, split memory_region_is_logging in two functions: one that returns a given bit from dirty_log_mask, and one that returns the entire mask. memory_region_is_logging gets an extra parameter so that the compiler flags misuse. While VGA-specific users (including the Xen listener!) will want to keep checking that bit, KVM and vhost check for "any bit except migration" (because migration is handled via the global start/stop listener callbacks). Backports commit 2d1a35bef0ed96b3f23535e459c552414ccdbafd from qemu
2018-02-13 13:41:40 +00:00
'memory_region_get_dirty_log_mask',
import
2015-08-21 07:04:50 +00:00
'memory_region_get_fd',
'memory_region_get_may_overlap',
'memory_region_get_priority',
memory: Implement memory_region_get_ram_addr with mr->ram_block Backports commit 7ebb2745acbb8d910eab07dc5f0aa01a4457703c from qemu
2018-02-21 13:00:50 +00:00
'memory_region_get_ram_addr',
import
2015-08-21 07:04:50 +00:00
'memory_region_get_ram_ptr',
'memory_region_get_size',
'memory_region_info',
'memory_region_init',
'memory_region_init_alias',
'memory_region_init_io',
memory: Replace skip_dump flag with ram_device Setting skip_dump on a MemoryRegion allows us to modify one specific code path, but the restriction we're trying to address encompasses more than that. If we have a RAM MemoryRegion backed by a physical device, it not only restricts our ability to dump that region, but also affects how we should manipulate it. Here we recognize that MemoryRegions do not change to sometimes allow dumps and other times not, so we replace setting the skip_dump flag with a new initializer so that we know exactly the type of region to which we're applying this behavior. Backports commit ca83f87a66d19fdaabf23d4f5ebb49396fe232c1 from qemu
2018-02-26 03:59:02 +00:00
'memory_region_init_ram_device_ptr',
memory: Rename memory_region_init_ram() to memory_region_init_ram_nomigrate() Rename memory_region_init_ram() to memory_region_init_ram_nomigrate(). This leaves the way clear for us to provide a memory_region_init_ram() which does handle migration. Backports commit 1cfe48c1ce219b60a9096312f7a61806fae64ab3 from qemu
2018-03-04 03:23:26 +00:00
'memory_region_init_ram_nomigrate',
import
2015-08-21 07:04:50 +00:00
'memory_region_init_ram_ptr',
'memory_region_init_reservation',
pc: resizeable ROM blocks This makes ROM blocks resizeable. This infrastructure is required for other functionality we have queued. Backports commit aaf03019175949eda5087329448b8a0033b89479 from qemu
2018-02-17 22:02:55 +00:00
'memory_region_init_resizeable_ram',
memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate() Rename memory_region_init_rom() to memory_region_init_rom_nomigrate() and memory_region_init_rom_device() to memory_region_init_rom_device_nomigrate(). Backports commit b59821a95bd1d7cb4697fd7748725c910582e0e7 from qemu
2018-03-04 03:28:41 +00:00
'memory_region_init_rom_nomigrate',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_region_initfn',
import
2015-08-21 07:04:50 +00:00
'memory_region_is_logging',
'memory_region_is_mapped',
memory: Replace skip_dump flag with ram_device Setting skip_dump on a MemoryRegion allows us to modify one specific code path, but the restriction we're trying to address encompasses more than that. If we have a RAM MemoryRegion backed by a physical device, it not only restricts our ability to dump that region, but also affects how we should manipulate it. Here we recognize that MemoryRegions do not change to sometimes allow dumps and other times not, so we replace setting the skip_dump flag with a new initializer so that we know exactly the type of region to which we're applying this behavior. Backports commit ca83f87a66d19fdaabf23d4f5ebb49396fe232c1 from qemu
2018-02-26 03:59:02 +00:00
'memory_region_is_ram_device',
import
2015-08-21 07:04:50 +00:00
'memory_region_is_unassigned',
'memory_region_name',
'memory_region_need_escape',
'memory_region_oldmmio_read_accessor',
'memory_region_oldmmio_write_accessor',
'memory_region_present',
'memory_region_read_accessor',
'memory_region_readd_subregion',
'memory_region_ref',
'memory_region_resolve_container',
'memory_region_rom_device_set_romd',
'memory_region_section_get_iotlb',
'memory_region_set_address',
'memory_region_set_alias_offset',
'memory_region_set_enabled',
'memory_region_set_readonly',
memory: add memory_region_set_size Add API to change MR size. Will be used internally for RAM resize. Backports commit e7af4c67300b3f9382e96f7a6741a5992116b2d2 from qemu
2018-02-17 21:02:13 +00:00
'memory_region_set_size',
import
2015-08-21 07:04:50 +00:00
'memory_region_size',
'memory_region_to_address_space',
'memory_region_transaction_begin',
'memory_region_transaction_commit',
'memory_region_unref',
'memory_region_update_container_subregions',
'memory_region_write_accessor',
'memory_region_wrong_endianness',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_register_types',
import
2015-08-21 07:04:50 +00:00
'memory_try_enable_merging',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'memory_unmap',
import
2015-08-21 07:04:50 +00:00
'module_call_init',
'module_load',
'mpidr_cp_reginfo',
'mpidr_read',
'msr_mask',
'mul128By64To192',
'mul128To256',
'mul64To128',
'muldiv64',
'neon_2rm_is_float_op',
'neon_2rm_sizes',
'neon_3r_sizes',
'neon_get_scalar',
'neon_load_reg',
'neon_load_reg64',
'neon_load_scratch',
'neon_ls_element_type',
'neon_reg_offset',
'neon_store_reg',
'neon_store_reg64',
'neon_store_scratch',
'new_ldst_label',
'next_list',
'normalizeFloat128Subnormal',
'normalizeFloat16Subnormal',
'normalizeFloat32Subnormal',
'normalizeFloat64Subnormal',
'normalizeFloatx80Subnormal',
'normalizeRoundAndPackFloat128',
'normalizeRoundAndPackFloat32',
'normalizeRoundAndPackFloat64',
'normalizeRoundAndPackFloatx80',
'not_v6_cp_reginfo',
'not_v7_cp_reginfo',
'not_v8_cp_reginfo',
'object_child_foreach',
qom: Add recursive version of object_child_for_each Useful for iterating through an entire QOM subtree. Backports commit d714b8de7747f20fe42e5716d1d44f91e2b891f4 from qemu
2018-02-15 16:13:21 +00:00
'object_child_foreach_recursive',
import
2015-08-21 07:04:50 +00:00
'object_class_foreach',
'object_class_foreach_tramp',
'object_class_get_list',
'object_class_get_list_tramp',
'object_class_get_parent',
'object_deinit',
'object_dynamic_cast',
'object_finalize',
'object_finalize_child_property',
'object_get_child_property',
qom: provide root container for internal objs We have object_get_objects_root() to keep user created objects, however no place for objects that will be used internally. Create such a container for internal objects. Backports commit 7c47c4ead75d0b733ee8f2f51fd1de0644cc1308 from qemu
2018-03-05 06:16:25 +00:00
'object_get_internal_root',
import
2015-08-21 07:04:50 +00:00
'object_get_link_property',
'object_get_root',
'object_init_with_type',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'object_initialize_with_type',
import
2015-08-21 07:04:50 +00:00
'object_instance_init',
'object_new_with_type',
'object_post_init_with_type',
'object_property_add_alias',
'object_property_add_link',
'object_property_add_uint16_ptr',
'object_property_add_uint32_ptr',
'object_property_add_uint64_ptr',
'object_property_add_uint8_ptr',
'object_property_allow_set_link',
'object_property_del',
'object_property_del_all',
'object_property_find',
'object_property_get',
'object_property_get_bool',
'object_property_get_int',
'object_property_get_link',
'object_property_get_qobject',
'object_property_get_str',
'object_property_get_type',
'object_property_is_child',
'object_property_set',
'object_property_set_description',
'object_property_set_link',
'object_property_set_qobject',
'object_release_link_property',
'object_resolve_abs_path',
'object_resolve_child_property',
'object_resolve_link',
'object_resolve_link_property',
'object_resolve_partial_path',
'object_resolve_path',
'object_resolve_path_component',
'object_resolve_path_type',
'object_set_link_property',
qom: API to get instance_size of a type Add an API object_type_get_size(const char *typename) that returns the instance_size of the give typename. Backports commit 3f97b53a682d2595747c926c00d78b9d406f1be0 from qemu
2018-02-24 23:59:25 +00:00
'object_type_get_instance_size',
import
2015-08-21 07:04:50 +00:00
'object_unparent',
'omap_cachemaint_write',
'omap_cp_reginfo',
'omap_threadid_write',
'omap_ticonfig_write',
'omap_wfi_write',
'op_bits',
'op_to_mov',
'op_to_movi',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'open_modeflags',
import
2015-08-21 07:04:50 +00:00
'output_type_enum',
'packFloat128',
'packFloat16',
'packFloat32',
'packFloat64',
'packFloatx80',
'page_find',
'page_find_alloc',
'page_flush_tb',
'page_flush_tb_1',
'page_init',
'page_size_init',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'par_write',
import
2015-08-21 07:04:50 +00:00
'parse_array',
'parse_error',
'parse_escape',
'parse_keyword',
'parse_literal',
'parse_object',
'parse_option_bool',
'parse_option_number',
'parse_option_size',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'parse_optional',
import
2015-08-21 07:04:50 +00:00
'parse_pair',
'parse_str',
'parse_type_bool',
'parse_type_int',
'parse_type_number',
'parse_type_size',
'parse_type_str',
'parse_value',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'parser_context_free',
'parser_context_new',
'parser_context_peek_token',
'parser_context_pop_token',
'parser_context_restore',
'parser_context_save',
import
2015-08-21 07:04:50 +00:00
'patch_reloc',
'phys_map_node_alloc',
'phys_map_node_reserve',
'phys_mem_alloc',
'phys_mem_set_alloc',
'phys_page_compact',
'phys_page_compact_all',
'phys_page_find',
'phys_page_set',
'phys_page_set_level',
'phys_section_add',
'phys_section_destroy',
'phys_sections_free',
'pickNaN',
'pickNaNMulAdd',
'pmccfiltr_write',
'pmccntr_read',
'pmccntr_sync',
'pmccntr_write',
'pmccntr_write32',
'pmcntenclr_write',
'pmcntenset_write',
'pmcr_write',
'pmintenclr_write',
'pmintenset_write',
'pmovsr_write',
'pmreg_access',
'pmsav5_cp_reginfo',
'pmsav5_data_ap_read',
'pmsav5_data_ap_write',
'pmsav5_insn_ap_read',
'pmsav5_insn_ap_write',
'pmuserenr_write',
'pmxevtyper_write',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'ppc_tb_set_jmp_target',
import
2015-08-21 07:04:50 +00:00
'print_type_bool',
'print_type_int',
'print_type_number',
'print_type_size',
'print_type_str',
softmmu: Add probe_write() Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Backports commit 3b4afc9e75ab1a95f33e41f462921093f8a109c4 from qemu
2018-02-27 17:17:15 +00:00
'probe_write',
import
2015-08-21 07:04:50 +00:00
'propagateFloat128NaN',
'propagateFloat32MulAddNaN',
'propagateFloat32NaN',
'propagateFloat64MulAddNaN',
'propagateFloat64NaN',
'propagateFloatx80NaN',
'property_get_alias',
'property_get_bool',
'property_get_str',
'property_get_uint16_ptr',
'property_get_uint32_ptr',
'property_get_uint64_ptr',
'property_get_uint8_ptr',
'property_release_alias',
'property_release_bool',
'property_release_str',
'property_resolve_alias',
'property_set_alias',
'property_set_bool',
'property_set_str',
'pstate_read',
'pstate_write',
'pxa250_initfn',
'pxa255_initfn',
'pxa260_initfn',
'pxa261_initfn',
'pxa262_initfn',
'pxa270a0_initfn',
'pxa270a1_initfn',
'pxa270b0_initfn',
'pxa270b1_initfn',
'pxa270c0_initfn',
'pxa270c5_initfn',
'qapi_dealloc_end_implicit_struct',
'qapi_dealloc_end_list',
'qapi_dealloc_end_struct',
'qapi_dealloc_get_visitor',
'qapi_dealloc_next_list',
'qapi_dealloc_pop',
'qapi_dealloc_push',
'qapi_dealloc_start_implicit_struct',
'qapi_dealloc_start_list',
'qapi_dealloc_start_struct',
'qapi_dealloc_start_union',
'qapi_dealloc_type_bool',
'qapi_dealloc_type_enum',
'qapi_dealloc_type_int',
'qapi_dealloc_type_number',
'qapi_dealloc_type_size',
'qapi_dealloc_type_str',
'qapi_dealloc_visitor_cleanup',
'qapi_dealloc_visitor_new',
'qapi_free_ErrorClassList',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'qapi_free_X86CPUFeatureWordInfo',
'qapi_free_X86CPUFeatureWordInfoList',
'qapi_free_X86CPURegister32List',
'qapi_free_boolList',
import
2015-08-21 07:04:50 +00:00
'qapi_free_int16List',
'qapi_free_int32List',
'qapi_free_int64List',
'qapi_free_int8List',
'qapi_free_intList',
'qapi_free_numberList',
'qapi_free_strList',
'qapi_free_uint16List',
'qapi_free_uint32List',
'qapi_free_uint64List',
'qapi_free_uint8List',
'qbool_destroy_obj',
'qbool_from_int',
'qbool_get_int',
'qbool_type',
'qbus_create',
'qbus_create_inplace',
'qbus_finalize',
'qbus_initfn',
'qbus_realize',
'qdev_create',
'qdev_get_type',
'qdev_register_types',
'qdev_set_parent_bus',
'qdev_try_create',
'qdict_add_key',
'qdict_array_split',
'qdict_clone_shallow',
'qdict_del',
'qdict_destroy_obj',
'qdict_entry_key',
'qdict_entry_value',
'qdict_extract_subqdict',
'qdict_find',
'qdict_first',
'qdict_flatten',
'qdict_flatten_qdict',
'qdict_flatten_qlist',
'qdict_get',
'qdict_get_bool',
'qdict_get_double',
'qdict_get_int',
'qdict_get_obj',
'qdict_get_qdict',
'qdict_get_qlist',
'qdict_get_str',
'qdict_get_try_bool',
'qdict_get_try_int',
'qdict_get_try_str',
'qdict_has_prefixed_entries',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'qdict_haskey',
import
2015-08-21 07:04:50 +00:00
'qdict_iter',
'qdict_join',
'qdict_new',
'qdict_next',
'qdict_next_entry',
qdict qlist: Make most helper macros functions The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h and qnum.h in the headers, but not qbool.h and qstring.h. Works, because we include those wherever the macros get used. Open-coding these helpers is of dubious value. Turn them into functions and drop the includes from the headers. This cleanup makes the number of objects depending on qapi/qmp/qnum.h from 4551 (out of 4743) to 46 in my "build everything" tree. For qapi/qmp/qnull.h, the number drops from 4552 to 21. Backports commit 15280c360e54a65e2c7be1a47bfbe41dce1ef986 from qemu
2018-03-08 13:29:56 +00:00
'qdict_put_bool',
'qdict_put_int',
'qdict_put_null',
import
2015-08-21 07:04:50 +00:00
'qdict_put_obj',
qdict qlist: Make most helper macros functions The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h and qnum.h in the headers, but not qbool.h and qstring.h. Works, because we include those wherever the macros get used. Open-coding these helpers is of dubious value. Turn them into functions and drop the includes from the headers. This cleanup makes the number of objects depending on qapi/qmp/qnum.h from 4551 (out of 4743) to 46 in my "build everything" tree. For qapi/qmp/qnull.h, the number drops from 4552 to 21. Backports commit 15280c360e54a65e2c7be1a47bfbe41dce1ef986 from qemu
2018-03-08 13:29:56 +00:00
'qdict_put_str',
qdict: Introduce qdict_rename_keys() A few block drivers will need to rename .bdrv_create options for their QAPIfication, so let's have a helper function for that. Backports commit bcebf102ccc3c6db327f341adc379fdf0673ca6b from qemu
2018-03-12 13:38:35 +00:00
'qdict_rename_keys',
import
2015-08-21 07:04:50 +00:00
'qdict_size',
'qdict_type',
'qemu_clock_get_us',
'qemu_clock_ptr',
'qemu_clocks',
'qemu_get_cpu',
'qemu_get_guest_memory_mapping',
'qemu_get_guest_simple_memory_mapping',
'qemu_get_ram_block',
'qemu_host_page_mask',
'qemu_host_page_size',
'qemu_init_vcpu',
'qemu_ld_helpers',
'qemu_log_enabled',
'qemu_log_vprintf',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'qemu_loglevel_mask',
exec: hide mr->ram_addr from qemu_get_ram_ptr users Let users of qemu_get_ram_ptr and qemu_ram_ptr_length pass in an address that is relative to the MemoryRegion. This basically means what address_space_translate returns. Because the semantics of the second parameter change, rename the function to qemu_map_ram_ptr. Backports commit 0878d0e11ba8013dd759c6921cbf05ba6a41bd71 from qemu
2018-02-24 21:10:07 +00:00
'qemu_map_ram_ptr',
import
2015-08-21 07:04:50 +00:00
'qemu_oom_check',
'qemu_parse_fd',
'qemu_ram_addr_from_host',
'qemu_ram_addr_from_host_nofail',
'qemu_ram_alloc',
'qemu_ram_alloc_from_ptr',
pc: resizeable ROM blocks This makes ROM blocks resizeable. This infrastructure is required for other functionality we have queued. Backports commit aaf03019175949eda5087329448b8a0033b89479 from qemu
2018-02-17 22:02:55 +00:00
'qemu_ram_alloc_resizeable',
qemu_ram_block_by_name Add a function to find a RAMBlock by name; use it in two of the places that already open code that loop; we've got another use later in postcopy. Backports commit e3dd74934f2d2c8c67083995928ff68e8c1d0030 from qemu
2018-02-17 22:58:36 +00:00
'qemu_ram_block_by_name',
qemu_ram_block_from_host Postcopy sends RAMBlock names and offsets over the wire (since it can't rely on the order of ramaddr being the same), and it starts out with HVA fault addresses from the kernel. qemu_ram_block_from_host translates a HVA into a RAMBlock, an offset in the RAMBlock and the global ram_addr_t value. Rewrite qemu_ram_addr_from_host to use qemu_ram_block_from_host. Provide qemu_ram_get_idstr since its the actual name text sent on the wire. Backports commit 422148d3e56c3c9a07c0cf36c1e0a0b76f09c357 from qemu
2018-02-17 22:52:30 +00:00
'qemu_ram_block_from_host',
import
2015-08-21 07:04:50 +00:00
'qemu_ram_foreach_block',
'qemu_ram_free',
qemu_ram_block_from_host Postcopy sends RAMBlock names and offsets over the wire (since it can't rely on the order of ramaddr being the same), and it starts out with HVA fault addresses from the kernel. qemu_ram_block_from_host translates a HVA into a RAMBlock, an offset in the RAMBlock and the global ram_addr_t value. Rewrite qemu_ram_addr_from_host to use qemu_ram_block_from_host. Provide qemu_ram_get_idstr since its the actual name text sent on the wire. Backports commit 422148d3e56c3c9a07c0cf36c1e0a0b76f09c357 from qemu
2018-02-17 22:52:30 +00:00
'qemu_ram_get_idstr',
RAMBlocks: qemu_ram_is_shared Provide a helper to say whether a RAMBlock was created as a shared mapping. Backports commit 463a4ac23bcf0f0b65c850fa66f5ae6e43edd243 from qemu
2018-03-02 18:04:57 +00:00
'qemu_ram_is_shared',
import
2015-08-21 07:04:50 +00:00
'qemu_ram_ptr_length',
'qemu_ram_remap',
pc: resizeable ROM blocks This makes ROM blocks resizeable. This infrastructure is required for other functionality we have queued. Backports commit aaf03019175949eda5087329448b8a0033b89479 from qemu
2018-02-17 22:02:55 +00:00
'qemu_ram_resize',
import
2015-08-21 07:04:50 +00:00
'qemu_ram_setup_dump',
'qemu_ram_unset_idstr',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'qemu_st_helpers',
qemu-common: Add missing string util functions
2018-02-15 13:29:50 +00:00
'qemu_strnlen',
'qemu_strsep',
tcg: add options for enabling MTTCG We know there will be cases where MTTCG won't work until additional work is done in the front/back ends to support. It will however be useful to be able to turn it on. As a result MTTCG will default to off unless the combination is supported. However the user can turn it on for the sake of testing. Backports commit 8d4e9146b3568022ea5730d92841345d41275d66 from qemu
2018-03-02 14:17:49 +00:00
'qemu_tcg_configure',
import
2015-08-21 07:04:50 +00:00
'qemu_tcg_init_vcpu',
'qemu_try_memalign',
'qentry_destroy',
'qerror_human',
'qerror_report',
'qerror_report_err',
'qfloat_destroy_obj',
'qfloat_from_double',
'qfloat_get_double',
'qfloat_type',
'qint_destroy_obj',
'qint_from_int',
'qint_get_int',
'qint_type',
qdict qlist: Make most helper macros functions The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h and qnum.h in the headers, but not qbool.h and qstring.h. Works, because we include those wherever the macros get used. Open-coding these helpers is of dubious value. Turn them into functions and drop the includes from the headers. This cleanup makes the number of objects depending on qapi/qmp/qnum.h from 4551 (out of 4743) to 46 in my "build everything" tree. For qapi/qmp/qnull.h, the number drops from 4552 to 21. Backports commit 15280c360e54a65e2c7be1a47bfbe41dce1ef986 from qemu
2018-03-08 13:29:56 +00:00
'qlist_append_bool',
'qlist_append_int',
'qlist_append_null',
import
2015-08-21 07:04:50 +00:00
'qlist_append_obj',
qdict qlist: Make most helper macros functions The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h and qnum.h in the headers, but not qbool.h and qstring.h. Works, because we include those wherever the macros get used. Open-coding these helpers is of dubious value. Turn them into functions and drop the includes from the headers. This cleanup makes the number of objects depending on qapi/qmp/qnum.h from 4551 (out of 4743) to 46 in my "build everything" tree. For qapi/qmp/qnull.h, the number drops from 4552 to 21. Backports commit 15280c360e54a65e2c7be1a47bfbe41dce1ef986 from qemu
2018-03-08 13:29:56 +00:00
'qlist_append_str',
import
2015-08-21 07:04:50 +00:00
'qlist_copy',
'qlist_copy_elem',
'qlist_destroy_obj',
'qlist_empty',
'qlist_entry_obj',
'qlist_first',
'qlist_iter',
'qlist_new',
'qlist_next',
'qlist_peek',
'qlist_pop',
'qlist_size',
'qlist_size_iter',
'qlist_type',
qlit: rename compare_litqobj_to_qobj() to qlit_equal_qobject() compare_litqobj_to_qobj() lacks a qlit_ prefix. Moreover, "compare" suggests -1, 0, +1 for less than, equal and greater than. The function actually returns non-zero for equal, zero for unequal. Rename to qlit_equal_qobject(). Its return type will be cleaned up in the next patch. Backports commit 60cc2eb7afd40b9cbaa35a5e0b54f365ac6e49f1 from qemu
2018-03-07 22:14:53 +00:00
'qlit_equal_qobject',
qapi: rename QmpInputVisitor to QObjectInputVisitor The QmpInputVisitor has no direct dependency on QMP. It is valid to use it anywhere that one has a QObject. Rename it to better reflect its functionality as a generic QObject to QAPI converter. The previous commit renamed the files, this one renames C identifiers. Backports commit 09e68369a88d7de0f988972bf28eec1b80cc47f9 from qemu
2018-02-26 20:53:02 +00:00
'qobject_input_end_implicit_struct',
'qobject_input_end_list',
'qobject_input_end_struct',
'qobject_input_get_next_type',
'qobject_input_get_object',
'qobject_input_get_visitor',
'qobject_input_next_list',
'qobject_input_optional',
'qobject_input_pop',
'qobject_input_push',
'qobject_input_start_implicit_struct',
'qobject_input_start_list',
'qobject_input_start_struct',
'qobject_input_type_bool',
'qobject_input_type_int',
'qobject_input_type_number',
'qobject_input_type_str',
'qobject_input_visitor_cleanup',
'qobject_input_visitor_new',
'qobject_input_visitor_new_strict',
qapi: rename QmpOutputVisitor to QObjectOutputVisitor The QmpOutputVisitor has no direct dependency on QMP. It is valid to use it anywhere that one wants a QObject. Rename it to better reflect its functionality as a generic QAPI to QObject converter. The commit before previous renamed the files, this one renames C identifiers. Backports commit 7d5e199ade76c53ec316ab6779800581bb47c50a from qemu
2018-02-27 12:53:17 +00:00
'qobject_output_add_obj',
'qobject_output_end_list',
'qobject_output_end_struct',
'qobject_output_first',
'qobject_output_get_qobject',
'qobject_output_get_visitor',
'qobject_output_last',
'qobject_output_next_list',
'qobject_output_pop',
'qobject_output_push_obj',
'qobject_output_start_list',
'qobject_output_start_struct',
'qobject_output_type_bool',
'qobject_output_type_int',
'qobject_output_type_number',
'qobject_output_type_str',
'qobject_output_visitor_cleanup',
'qobject_output_visitor_new',
import
2015-08-21 07:04:50 +00:00
'qobject_decref',
'qobject_to_qbool',
'qobject_to_qdict',
'qobject_to_qfloat',
'qobject_to_qint',
'qobject_to_qlist',
'qobject_to_qstring',
'qobject_type',
'qstring_append',
'qstring_append_chr',
'qstring_append_int',
'qstring_destroy_obj',
'qstring_from_escaped_str',
'qstring_from_str',
'qstring_from_substr',
'qstring_get_length',
'qstring_get_str',
'qstring_new',
'qstring_type',
'ram_block_add',
'ram_size',
'range_compare',
'range_covers_byte',
'range_get_last',
'range_merge',
'ranges_can_merge',
'raw_read',
'raw_write',
'rcon',
'read_raw_cp_reg',
'recip_estimate',
'recip_sqrt_estimate',
'register_cp_regs_for_features',
'register_multipage',
'register_subpage',
'register_tm_clones',
'register_types_object',
'regnames',
'render_memory_region',
'reset_all_temps',
'reset_temp',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'restore_state_to_opc',
'resume_all_vcpus',
import
2015-08-21 07:04:50 +00:00
'rol32',
'rol64',
'ror32',
'ror64',
'roundAndPackFloat128',
'roundAndPackFloat16',
'roundAndPackFloat32',
'roundAndPackFloat64',
'roundAndPackFloatx80',
'roundAndPackInt32',
'roundAndPackInt64',
'roundAndPackUint64',
'round_to_inf',
'run_on_cpu',
's0',
's1',
'sa1100_initfn',
'sa1110_initfn',
'save_globals',
'scr_write',
'sctlr_write',
'set_bit',
'set_bits',
'set_default_nan_mode',
'set_feature',
'set_float_detect_tininess',
'set_float_exception_flags',
'set_float_rounding_mode',
'set_flush_inputs_to_zero',
'set_flush_to_zero',
cpu: Support a target CPU having a variable page size Support target CPUs having a page size which isn't knownn at compile time. To use this, the CPU implementation should: * define TARGET_PAGE_BITS_VARY * not define TARGET_PAGE_BITS * define TARGET_PAGE_BITS_MIN to the smallest value it might possibly want for TARGET_PAGE_BITS * call set_preferred_target_page_bits() in its realize function to indicate the actual preferred target page size for the CPU (and report any error from it) In CONFIG_USER_ONLY, the CPU implementation should continue to define TARGET_PAGE_BITS appropriately for the guest OS page size. Machines which want to take advantage of having the page size something larger than TARGET_PAGE_BITS_MIN must set the MachineClass minimum_page_bits field to a value which they guarantee will be no greater than the preferred page size for any CPU they create. Note that changing the target page size by setting minimum_page_bits is a migration compatibility break for that machine. For debugging purposes, attempts to use TARGET_PAGE_SIZE before it has been finally confirmed will assert. Backports commit 20bccb82ff3ea09bcb7c4ee226d3160cab15f7da from qemu
2018-02-26 16:54:41 +00:00
'set_preferred_target_page_bits',
import
2015-08-21 07:04:50 +00:00
'set_swi_errno',
'sextract32',
'sextract64',
'shift128ExtraRightJamming',
'shift128Right',
'shift128RightJamming',
'shift32RightJamming',
'shift64ExtraRightJamming',
'shift64RightJamming',
'shifter_out_im',
'shortShift128Left',
'shortShift192Left',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'simd_desc',
import
2015-08-21 07:04:50 +00:00
'simple_mpu_ap_bits',
'size_code_gen_buffer',
'softmmu_lock_user',
'softmmu_lock_user_string',
'softmmu_tget32',
'softmmu_tget8',
'softmmu_tput32',
'softmmu_unlock_user',
'sort_constraints',
'sp_el0_access',
'spsel_read',
'spsel_write',
'start_list',
'stb_p',
'stb_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stb_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stl_be_p',
'stl_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stl_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stl_he_p',
'stl_le_p',
'stl_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stl_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stl_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stl_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stl_phys_internal',
'stl_phys_notdirty',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stl_phys_notdirty_cached',
import
2015-08-21 07:04:50 +00:00
'store_cpu_offset',
'store_reg',
'store_reg_bx',
'store_reg_from_load',
'stq_be_p',
'stq_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stq_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stq_he_p',
'stq_le_p',
'stq_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stq_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stq_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stq_phys_cached',
import
2015-08-21 07:04:50 +00:00
'string_input_get_visitor',
'string_input_visitor_cleanup',
'string_input_visitor_new',
qemu-common: Add missing string util functions
2018-02-15 13:29:50 +00:00
'stristart',
import
2015-08-21 07:04:50 +00:00
'strongarm_cp_reginfo',
qemu-common: Add missing string util functions
2018-02-15 13:29:50 +00:00
'strpadcpy',
import
2015-08-21 07:04:50 +00:00
'strstart',
'stw_be_p',
'stw_be_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stw_be_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stw_he_p',
'stw_le_p',
'stw_le_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stw_le_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stw_phys',
exec: introduce MemoryRegionCache Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 15:10:15 +00:00
'stw_phys_cached',
import
2015-08-21 07:04:50 +00:00
'stw_phys_internal',
'sub128',
'sub16_sat',
'sub16_usat',
'sub192',
'sub8_sat',
'sub8_usat',
'subFloat128Sigs',
'subFloat32Sigs',
'subFloat64Sigs',
'subFloatx80Sigs',
'subpage_accepts',
'subpage_init',
'subpage_ops',
'subpage_read',
'subpage_register',
'subpage_write',
'suffix_mul',
'swap_commutative',
'swap_commutative2',
'switch_mode',
'syn_aa32_bkpt',
'syn_aa32_hvc',
'syn_aa32_smc',
'syn_aa32_svc',
'syn_breakpoint',
'syn_cp14_rrt_trap',
'syn_cp14_rt_trap',
'syn_cp15_rrt_trap',
'syn_cp15_rt_trap',
'syn_data_abort',
'syn_fp_access_trap',
'syn_insn_abort',
'syn_swstep',
'syn_uncategorized',
'syn_watchpoint',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'sync_globals',
import
2015-08-21 07:04:50 +00:00
'syscall_err',
'system_bus_class_init',
'system_bus_info',
't2ee_cp_reginfo',
'table_logic_cc',
target-arm: add async excp target_el function Adds a dedicated function and a lookup table for determining the target exception level of IRQ and FIQ exceptions. The lookup table is taken from the ARMv7 and ARMv8 specification exception routing tables. Backports commit 0eeb17d618361a0f4faddc160e33598b23da6dd5 from qemu
2018-02-11 22:42:00 +00:00
'target_el_table',
import
2015-08-21 07:04:50 +00:00
'target_parse_constraint',
'target_words_bigendian',
'tb_alloc',
'tb_alloc_page',
'tb_check_watchpoint',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tb_cleanup',
import
2015-08-21 07:04:50 +00:00
'tb_find_fast',
'tb_find_pc',
'tb_find_slow',
'tb_flush',
'tb_flush_jmp_cache',
'tb_gen_code',
'tb_hash_remove',
tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptr Instead of exporting goto_ptr directly to TCG frontends, export tcg_gen_lookup_and_goto_ptr(), which calls goto_ptr with the pointer returned by the lookup_tb_ptr() helper. This is the only use case we have for goto_ptr and lookup_tb_ptr, so having this function is very convenient. Furthermore, it trivially allows us to avoid calling the lookup helper if goto_ptr is not implemented by the backend. Backports commit cedbcb01529cb6cf9a2289cdbebbc63f6149fc18 from qemu
2018-03-03 01:56:29 +00:00
'tb_htable_lookup',
import
2015-08-21 07:04:50 +00:00
'tb_invalidate_phys_addr',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tb_invalidate_phys_page_fast',
import
2015-08-21 07:04:50 +00:00
'tb_invalidate_phys_page_range',
'tb_invalidate_phys_range',
'tb_jmp_cache_hash_func',
'tb_jmp_cache_hash_page',
'tb_jmp_remove',
'tb_link_page',
'tb_page_remove',
'tb_phys_hash_func',
'tb_phys_invalidate',
exec-all: rename tb_free to tb_remove We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Backports commit be1e01171b556807198c84feac7cf4bca0d904c2 from qemu
2018-03-13 20:20:32 +00:00
'tb_remove',
import
2015-08-21 07:04:50 +00:00
'tb_reset_jump',
'tb_set_jmp_target',
'tcg_accel_class_init',
'tcg_accel_type',
'tcg_add_param_i32',
'tcg_add_param_i64',
'tcg_add_target_add_op_defs',
'tcg_allowed',
tcg/i386: Add vector operations The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Backports commit 770c2fc7bb70804ae9869995fd02dadd6d7656ac from qemu
2018-03-06 21:20:28 +00:00
'tcg_can_emit_vec_op',
import
2015-08-21 07:04:50 +00:00
'tcg_canonicalize_memop',
'tcg_commit',
'tcg_cond_to_jcc',
'tcg_const_i32',
'tcg_const_i64',
'tcg_const_local_i32',
'tcg_const_local_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_const_ones_vec',
'tcg_const_ones_vec_matching',
'tcg_const_zeros_vec',
'tcg_const_zeros_vec_matching',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_constant_folding',
import
2015-08-21 07:04:50 +00:00
'tcg_context_init',
'tcg_cpu_exec',
'tcg_current_code_size',
'tcg_dump_info',
'tcg_dump_ops',
tcg: Dynamically allocate TCGOps With no fixed array allocation, we can't overflow a buffer. This will be important as optimizations related to host vectors may expand the number of ops used. Use QTAILQ to link the ops together. Backports commit 15fa08f8451babc88d733bd411d4c94976f9d0f8 from qemu
2018-03-05 21:01:13 +00:00
'tcg_emit_op',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_enabled',
import
2015-08-21 07:04:50 +00:00
'tcg_exec_all',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_exec_init',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_expand_vec_op',
import
2015-08-21 07:04:50 +00:00
'tcg_find_helper',
cpu: Introduce a wrapper for tlb_flush() that can be used in common code Commit 1f5c00cfdb8114c ("qom/cpu: move tlb_flush to cpu_common_reset") moved the call to tlb_flush() from the target-specific reset handlers into the common code qom/cpu.c file, and protected the call with "#ifdef CONFIG_SOFTMMU" to avoid that it is called for linux-user only targets. But since qom/cpu.c is common code, CONFIG_SOFTMMU is *never* defined here, so the tlb_flush() was simply never executed anymore. Fix it by introducing a wrapper for tlb_flush() in a file that is re-compiled for each target, i.e. in translate-all.c. Backports commit 2cd53943115be5118b5b2d4b80ee0a39c94c4f73 from qemu
2018-03-04 02:22:27 +00:00
'tcg_flush_softmmu_tlb',
import
2015-08-21 07:04:50 +00:00
'tcg_func_start',
'tcg_gen_abs_i32',
'tcg_gen_add2_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_add2_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_add_i32',
'tcg_gen_add_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_add_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_addi_i32',
'tcg_gen_addi_i64',
'tcg_gen_and_i32',
'tcg_gen_and_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_and_vec',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_andc_i32',
'tcg_gen_andc_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_andc_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_andi_i32',
'tcg_gen_andi_i64',
tcg: Add atomic helpers Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Backports commit c482cb117cc418115ca9c6d21a7a2315414c0a40 from qemu
2018-02-27 17:47:33 +00:00
'tcg_gen_atomic_add_fetch_i32',
'tcg_gen_atomic_add_fetch_i64',
'tcg_gen_atomic_and_fetch_i32',
'tcg_gen_atomic_and_fetch_i64',
'tcg_gen_atomic_cmpxchg_i32',
'tcg_gen_atomic_cmpxchg_i64',
'tcg_gen_atomic_fetch_add_i32',
'tcg_gen_atomic_fetch_add_i64',
'tcg_gen_atomic_fetch_and_i32',
'tcg_gen_atomic_fetch_and_i64',
'tcg_gen_atomic_fetch_or_i32',
'tcg_gen_atomic_fetch_or_i64',
'tcg_gen_atomic_fetch_xor_i32',
'tcg_gen_atomic_fetch_xor_i64',
'tcg_gen_atomic_or_fetch_i32',
'tcg_gen_atomic_or_fetch_i64',
'tcg_gen_atomic_xchg_i32',
'tcg_gen_atomic_xchg_i64',
'tcg_gen_atomic_xor_fetch_i32',
'tcg_gen_atomic_xor_fetch_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_br',
'tcg_gen_brcond_i32',
'tcg_gen_brcond_i64',
'tcg_gen_brcondi_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_brcondi_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_bswap16_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_bswap16_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_bswap32_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_bswap32_i64',
'tcg_gen_bswap64_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_callN',
tcg: Add helpers for clrsb The number of actual invocations does not warrent an opcode, and the backends generating it. But at least we can eliminate redundant helpers. Backports commit 086920c2c8008f125fd38781072fa25c3ad158ea from qemu
2018-03-01 23:12:18 +00:00
'tcg_gen_clrsb_i32',
'tcg_gen_clrsb_i64',
tcg: Add clz and ctz opcodes Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu
2018-03-01 20:53:35 +00:00
'tcg_gen_clz_i32',
'tcg_gen_clz_i64',
'tcg_gen_clzi_i32',
'tcg_gen_clzi_i64',
tcg: Add generic vector ops for comparisons Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 19:07:42 +00:00
'tcg_gen_cmp_vec',
tcg: Add opcode for ctpop The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Backports commit a768e4e99247911f00c5c0267c12d4e207d5f6cc from qemu
2018-03-01 23:21:05 +00:00
'tcg_gen_ctpop_i32',
'tcg_gen_ctpop_i64',
tcg: Add clz and ctz opcodes Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu
2018-03-01 20:53:35 +00:00
'tcg_gen_ctz_i32',
'tcg_gen_ctz_i64',
'tcg_gen_ctzi_i32',
'tcg_gen_ctzi_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_code',
'tcg_gen_concat_i32_i64',
'tcg_gen_deposit_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_deposit_i64',
tcg: Add deposit_z expander While we don't require a new opcode, it is handy to have an expander that knows the first source is zero. Backports commit 07cc68d52852bf47dea7c402b46ddd28248d4212 from qemu
2018-03-01 18:28:18 +00:00
'tcg_gen_deposit_z_i32',
'tcg_gen_deposit_z_i64',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_discard_i64',
'tcg_gen_div_i32',
'tcg_gen_div_i64',
'tcg_gen_divu_i32',
'tcg_gen_divu_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_dup8i_vec',
'tcg_gen_dup16i_vec',
'tcg_gen_dup32i_vec',
'tcg_gen_dup64i_vec',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_dupi_vec',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_dup_i32_vec',
'tcg_gen_dup_i64_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_eqv_i32',
'tcg_gen_eqv_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_exit_tb',
'tcg_gen_ext16s_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ext16s_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ext16u_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ext16u_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ext32s_i64',
'tcg_gen_ext32u_i64',
'tcg_gen_ext8s_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ext8s_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ext8u_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ext8u_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ext_i32_i64',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_extr32_i64',
'tcg_gen_extr_i64_i32',
tcg: Add field extraction primitives Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Backports commit 7ec8bab3deae643b1ce579c2d65a244f30708330 from qemu
2018-03-01 18:13:49 +00:00
'tcg_gen_extract_i32',
'tcg_gen_extract_i64',
tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Backports commit 609ad70562793937257c89d07bf7c1370b9fc9aa from qemu
2018-02-11 03:57:27 +00:00
'tcg_gen_extrh_i64_i32',
'tcg_gen_extrl_i64_i32',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_2',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_gvec_2i',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_2i_ool',
'tcg_gen_gvec_2s',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_2_ool',
'tcg_gen_gvec_2_ptr',
'tcg_gen_gvec_3',
'tcg_gen_gvec_3_ool',
'tcg_gen_gvec_3_ptr',
'tcg_gen_gvec_4',
'tcg_gen_gvec_4_ool',
'tcg_gen_gvec_4_ptr',
'tcg_gen_gvec_5_ool',
'tcg_gen_gvec_add',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_addi',
'tcg_gen_gvec_adds',
'tcg_gen_gvec_adds8',
'tcg_gen_gvec_adds16',
'tcg_gen_gvec_adds32',
'tcg_gen_gvec_adds64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_and',
'tcg_gen_gvec_andc',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_andi',
'tcg_gen_gvec_ands',
tcg: Add generic vector ops for comparisons Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 19:07:42 +00:00
'tcg_gen_gvec_cmp',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_dup8i',
'tcg_gen_gvec_dup16i',
'tcg_gen_gvec_dup32i',
'tcg_gen_gvec_dup64i',
'tcg_gen_gvec_dup_i32',
'tcg_gen_gvec_dup_i64',
'tcg_gen_gvec_dup_mem',
'tcg_gen_gvec_mov',
tcg: Add generic vector ops for multiplication Backports commit 3774030a3e523689df24a7ed22854ce7a06b0116 from qemu
2018-03-06 19:36:48 +00:00
'tcg_gen_gvec_mul',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_muli',
'tcg_gen_gvec_muls',
'tcg_gen_gvec_muls8',
'tcg_gen_gvec_muls16',
'tcg_gen_gvec_muls32',
'tcg_gen_gvec_muls64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_neg',
'tcg_gen_gvec_not',
'tcg_gen_gvec_or',
'tcg_gen_gvec_orc',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_ori',
'tcg_gen_gvec_ors',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_gvec_sari',
'tcg_gen_gvec_shli',
'tcg_gen_gvec_shri',
tcg: Add generic helpers for saturating arithmetic No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive. Backports commit f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd from qemu
2018-03-06 19:46:05 +00:00
'tcg_gen_gvec_ssadd',
'tcg_gen_gvec_sssub',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_sub',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_subs',
'tcg_gen_gvec_subs8',
'tcg_gen_gvec_subs16',
'tcg_gen_gvec_subs32',
'tcg_gen_gvec_subs64',
tcg: Add generic helpers for saturating arithmetic No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive. Backports commit f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd from qemu
2018-03-06 19:46:05 +00:00
'tcg_gen_gvec_usadd',
'tcg_gen_gvec_ussub',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_gvec_xor',
tcg: Add generic vector helpers with a scalar operand Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 19:54:25 +00:00
'tcg_gen_gvec_xori',
'tcg_gen_gvec_xors',
tcg: Rename debug_insn_start to insn_start With an eye toward making it mandatory. Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
2018-02-11 17:31:22 +00:00
'tcg_gen_insn_start',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ld16s_i64',
'tcg_gen_ld16u_i64',
'tcg_gen_ld32s_i64',
'tcg_gen_ld32u_i64',
'tcg_gen_ld8s_i64',
'tcg_gen_ld8u_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ld_i32',
'tcg_gen_ld_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_ld_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ldst_op_i32',
'tcg_gen_ldst_op_i64',
tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptr Instead of exporting goto_ptr directly to TCG frontends, export tcg_gen_lookup_and_goto_ptr(), which calls goto_ptr with the pointer returned by the lookup_tb_ptr() helper. This is the only use case we have for goto_ptr and lookup_tb_ptr, so having this function is very convenient. Furthermore, it trivially allows us to avoid calling the lookup helper if goto_ptr is not implemented by the backend. Backports commit cedbcb01529cb6cf9a2289cdbebbc63f6149fc18 from qemu
2018-03-03 01:56:29 +00:00
'tcg_gen_lookup_and_goto_ptr',
Introduce TCGOpcode for memory barrier This commit introduces the TCGOpcode for memory barrier instruction. This opcode takes an argument which is the type of memory barrier which should be generated. Backports commit f65e19bc2c9e8358e634d309606144ac2a3c2936 from qemu
2018-02-26 07:59:13 +00:00
'tcg_gen_mb',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_mov_i32',
'tcg_gen_mov_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_mov_vec',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_movcond_i32',
'tcg_gen_movcond_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_movi_i32',
'tcg_gen_movi_i64',
'tcg_gen_mul_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_mul_i64',
tcg: Add generic vector ops for multiplication Backports commit 3774030a3e523689df24a7ed22854ce7a06b0116 from qemu
2018-03-06 19:36:48 +00:00
'tcg_gen_mul_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_muli_i32',
'tcg_gen_muli_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_muls2_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_muls2_i64',
tcg: Add tcg_gen_mulsu2_{i32,i64,tl} This multiply has one signed input and one unsigned input, producing the full double-width result. Backports commit 5087abfb7dfd1d368ae6939420057036b4d8e509 from qemu
2018-03-01 13:37:11 +00:00
'tcg_gen_mulsu2_i32',
'tcg_gen_mulsu2_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_mulu2_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_mulu2_i64',
'tcg_gen_nand_i32',
'tcg_gen_nand_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_neg_i32',
'tcg_gen_neg_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_neg_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_nor_i32',
'tcg_gen_nor_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_nor_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_not_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_not_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_not_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_op1',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op1i',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_op2',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op2_i32',
'tcg_gen_op2_i64',
'tcg_gen_op2i_i32',
'tcg_gen_op2i_i64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_op3',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op3_i32',
'tcg_gen_op3_i64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_op4',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op4_i32',
'tcg_gen_op4i_i32',
'tcg_gen_op4ii_i32',
'tcg_gen_op4ii_i64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_op5',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op5ii_i32',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_op6',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_op6_i32',
'tcg_gen_op6i_i32',
'tcg_gen_op6i_i64',
'tcg_gen_or_i32',
'tcg_gen_or_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_or_vec',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_orc_i32',
'tcg_gen_orc_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_orc_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_ori_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_ori_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_qemu_ld_i32',
'tcg_gen_qemu_ld_i64',
'tcg_gen_qemu_st_i32',
'tcg_gen_qemu_st_i64',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_rem_i32',
'tcg_gen_rem_i64',
'tcg_gen_remu_i32',
'tcg_gen_remu_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_rotl_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_rotl_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_rotli_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_rotli_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_rotr_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_rotr_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_rotri_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_rotri_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_sar_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_sar_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_sari_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_sari_i64',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_sari_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_setcond_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_setcond_i64',
'tcg_gen_setcondi_i32',
'tcg_gen_setcondi_i64',
tcg: Add field extraction primitives Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Backports commit 7ec8bab3deae643b1ce579c2d65a244f30708330 from qemu
2018-03-01 18:13:49 +00:00
'tcg_gen_sextract_i32',
'tcg_gen_sextract_i64',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_gen_shifti_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_shl_i32',
'tcg_gen_shl_i64',
'tcg_gen_shli_i32',
'tcg_gen_shli_i64',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_shli_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_shr_i32',
'tcg_gen_shr_i64',
'tcg_gen_shri_i32',
'tcg_gen_shri_i64',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_shri_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_st_i32',
'tcg_gen_st_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_st_vec',
'tcg_gen_stl_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_sub2_i32',
'tcg_gen_sub2_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_sub_i32',
'tcg_gen_sub_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_sub_vec',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_subfi_i32',
'tcg_gen_subfi_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_subi_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_subi_i64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_vec_add8_i64',
'tcg_gen_vec_add16_i64',
'tcg_gen_vec_add32_i64',
'tcg_gen_vec_neg8_i64',
'tcg_gen_vec_neg16_i64',
'tcg_gen_vec_neg32_i64',
tcg: Add generic vector ops for constant shifts Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 18:45:25 +00:00
'tcg_gen_vec_sar8i_i64',
'tcg_gen_vec_sar16i_i64',
'tcg_gen_vec_shl8i_i64',
'tcg_gen_vec_shl16i_i64',
'tcg_gen_vec_shr8i_i64',
'tcg_gen_vec_shr16i_i64',
tcg: Add generic vector expanders Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 17:19:54 +00:00
'tcg_gen_vec_sub8_i64',
'tcg_gen_vec_sub16_i64',
'tcg_gen_vec_sub32_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_gen_xor_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_gen_xori_i32',
tcg: Move some opcode generation functions out of line Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.
2018-02-08 20:19:28 +00:00
'tcg_gen_xori_i64',
import
2015-08-21 07:04:50 +00:00
'tcg_get_arg_str_i32',
'tcg_get_arg_str_i64',
'tcg_get_arg_str_idx',
'tcg_global_mem_new_i32',
'tcg_global_mem_new_i64',
'tcg_global_mem_new_internal',
'tcg_global_reg_new_internal',
'tcg_handle_interrupt',
'tcg_init',
'tcg_invert_cond',
'tcg_la_bb_end',
Fix possible wrong conditional branch in generated host code by fixing the tcg_liveness_analysis(). Refer to https://github.com/unicorn-engine/unicorn/issues/287 for further info.
2015-12-21 10:01:01 +00:00
'tcg_la_br_end',
import
2015-08-21 07:04:50 +00:00
'tcg_la_func_end',
'tcg_liveness_analysis',
'tcg_malloc',
'tcg_malloc_internal',
'tcg_op_defs_org',
tcg: Lower indirect registers in a separate pass Rather than rely on recursion during the middle of register allocation, lower indirect registers to loads and stores off the indirect base into plain temps. For an x86_64 host, with sufficient registers, this results in identical code, modulo the actual register assignments. For an i686 host, with insufficient registers, this means that temps can be (temporarily) spilled to the stack in order to satisfy an allocation. This as opposed to the possibility of not being able to spill, to allocate a register for the indirect base, in order to perform a spill. Backports commit 5a18407f55ade924aa6397c9a043a9ffd59645fe from qemu
2018-02-26 03:23:00 +00:00
'tcg_op_insert_after',
'tcg_op_insert_before',
tcg: Remove opcodes instead of noping them out With the linked list scheme we need not leave nops in the stream that we need to process later. Backports commit 0c627cdca20155753a536c51385abb73941a59a0 from qemu
2018-02-09 18:03:25 +00:00
'tcg_op_remove',
tcg: Add tcg_op_supported Backports commit be0f34b5840312bbe9627c2b9f68a25f32903dae from qemu
2018-03-05 04:20:12 +00:00
'tcg_op_supported',
import
2015-08-21 07:04:50 +00:00
'tcg_opt_gen_mov',
'tcg_opt_gen_movi',
'tcg_optimize',
'tcg_out16',
'tcg_out32',
'tcg_out64',
'tcg_out8',
'tcg_out_addi',
'tcg_out_branch',
'tcg_out_brcond32',
'tcg_out_brcond64',
'tcg_out_bswap32',
'tcg_out_bswap64',
'tcg_out_call',
'tcg_out_cmp',
tcg: introduce regions to split code_gen_buffer This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=83885014 nb_tbs=154739 avg_tb_size=357 qemu: flush code_size=83884902 nb_tbs=153136 avg_tb_size=363 qemu: flush code_size=83885014 nb_tbs=152777 avg_tb_size=364 qemu: flush code_size=83884950 nb_tbs=150057 avg_tb_size=373 qemu: flush code_size=83884998 nb_tbs=150234 avg_tb_size=373 qemu: flush code_size=83885014 nb_tbs=154009 avg_tb_size=360 qemu: flush code_size=83885014 nb_tbs=151007 avg_tb_size=370 qemu: flush code_size=83885014 nb_tbs=151816 avg_tb_size=367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=76328008 nb_tbs=141040 avg_tb_size=356 qemu: flush code_size=75366534 nb_tbs=138000 avg_tb_size=361 qemu: flush code_size=76864546 nb_tbs=140653 avg_tb_size=361 qemu: flush code_size=76309084 nb_tbs=135945 avg_tb_size=375 qemu: flush code_size=74581856 nb_tbs=132909 avg_tb_size=375 qemu: flush code_size=73927256 nb_tbs=135616 avg_tb_size=360 qemu: flush code_size=78629426 nb_tbs=142896 avg_tb_size=365 qemu: flush code_size=76667052 nb_tbs=138508 avg_tb_size=368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=21936504 nb_tbs=40570 avg_tb_size=354 qemu: flush code_size=11472174 nb_tbs=20633 avg_tb_size=370 qemu: flush code_size=11603976 nb_tbs=21059 avg_tb_size=365 qemu: flush code_size=23254872 nb_tbs=41243 avg_tb_size=377 qemu: flush code_size=28289496 nb_tbs=52057 avg_tb_size=358 qemu: flush code_size=43605160 nb_tbs=78896 avg_tb_size=367 qemu: flush code_size=45166552 nb_tbs=82158 avg_tb_size=364 qemu: flush code_size=63289640 nb_tbs=116494 avg_tb_size=358 qemu: flush code_size=51389960 nb_tbs=93937 avg_tb_size=362 qemu: flush code_size=59665928 nb_tbs=107063 avg_tb_size=372 qemu: flush code_size=38380824 nb_tbs=68597 avg_tb_size=374 qemu: flush code_size=44884568 nb_tbs=79901 avg_tb_size=376 qemu: flush code_size=50782632 nb_tbs=90681 avg_tb_size=374 qemu: flush code_size=39848888 nb_tbs=71433 avg_tb_size=372 qemu: flush code_size=64708840 nb_tbs=119052 avg_tb_size=359 qemu: flush code_size=49830008 nb_tbs=90992 avg_tb_size=362 qemu: flush code_size=68372408 nb_tbs=123442 avg_tb_size=368 qemu: flush code_size=33555560 nb_tbs=59514 avg_tb_size=378 qemu: flush code_size=44748344 nb_tbs=80974 avg_tb_size=367 qemu: flush code_size=37104248 nb_tbs=67609 avg_tb_size=364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Backports commit e8feb96fcc6c16eab8923332e86ff4ef0e2ac276 from qemu
2018-03-14 15:14:31 +00:00
'tcg_code_capacity',
'tcg_code_size',
import
2015-08-21 07:04:50 +00:00
'tcg_out_ext16s',
'tcg_out_ext16u',
'tcg_out_ext32s',
'tcg_out_ext32u',
'tcg_out_ext8s',
'tcg_out_ext8u',
'tcg_out_jmp',
'tcg_out_jxx',
'tcg_out_label',
'tcg_out_ld',
'tcg_out_modrm',
'tcg_out_modrm_offset',
'tcg_out_modrm_sib_offset',
'tcg_out_mov',
'tcg_out_movcond32',
'tcg_out_movcond64',
'tcg_out_movi',
'tcg_out_op',
'tcg_out_pop',
'tcg_out_push',
'tcg_out_qemu_ld',
'tcg_out_qemu_ld_direct',
'tcg_out_qemu_ld_slow_path',
'tcg_out_qemu_st',
'tcg_out_qemu_st_direct',
'tcg_out_qemu_st_slow_path',
'tcg_out_reloc',
'tcg_out_rolw_8',
'tcg_out_setcond32',
'tcg_out_setcond64',
'tcg_out_shifti',
'tcg_out_st',
'tcg_out_tb_finalize',
'tcg_out_tb_init',
'tcg_out_tlb_load',
'tcg_out_vex_modrm',
'tcg_patch32',
'tcg_patch8',
'tcg_pcrel_diff',
'tcg_pool_reset',
'tcg_prologue_init',
'tcg_ptr_byte_diff',
'tcg_reg_alloc',
'tcg_reg_alloc_bb_end',
'tcg_reg_alloc_call',
'tcg_reg_alloc_mov',
'tcg_reg_alloc_movi',
'tcg_reg_alloc_op',
'tcg_reg_alloc_start',
'tcg_reg_free',
'tcg_reg_sync',
tcg: introduce regions to split code_gen_buffer This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=83885014 nb_tbs=154739 avg_tb_size=357 qemu: flush code_size=83884902 nb_tbs=153136 avg_tb_size=363 qemu: flush code_size=83885014 nb_tbs=152777 avg_tb_size=364 qemu: flush code_size=83884950 nb_tbs=150057 avg_tb_size=373 qemu: flush code_size=83884998 nb_tbs=150234 avg_tb_size=373 qemu: flush code_size=83885014 nb_tbs=154009 avg_tb_size=360 qemu: flush code_size=83885014 nb_tbs=151007 avg_tb_size=370 qemu: flush code_size=83885014 nb_tbs=151816 avg_tb_size=367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=76328008 nb_tbs=141040 avg_tb_size=356 qemu: flush code_size=75366534 nb_tbs=138000 avg_tb_size=361 qemu: flush code_size=76864546 nb_tbs=140653 avg_tb_size=361 qemu: flush code_size=76309084 nb_tbs=135945 avg_tb_size=375 qemu: flush code_size=74581856 nb_tbs=132909 avg_tb_size=375 qemu: flush code_size=73927256 nb_tbs=135616 avg_tb_size=360 qemu: flush code_size=78629426 nb_tbs=142896 avg_tb_size=365 qemu: flush code_size=76667052 nb_tbs=138508 avg_tb_size=368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=21936504 nb_tbs=40570 avg_tb_size=354 qemu: flush code_size=11472174 nb_tbs=20633 avg_tb_size=370 qemu: flush code_size=11603976 nb_tbs=21059 avg_tb_size=365 qemu: flush code_size=23254872 nb_tbs=41243 avg_tb_size=377 qemu: flush code_size=28289496 nb_tbs=52057 avg_tb_size=358 qemu: flush code_size=43605160 nb_tbs=78896 avg_tb_size=367 qemu: flush code_size=45166552 nb_tbs=82158 avg_tb_size=364 qemu: flush code_size=63289640 nb_tbs=116494 avg_tb_size=358 qemu: flush code_size=51389960 nb_tbs=93937 avg_tb_size=362 qemu: flush code_size=59665928 nb_tbs=107063 avg_tb_size=372 qemu: flush code_size=38380824 nb_tbs=68597 avg_tb_size=374 qemu: flush code_size=44884568 nb_tbs=79901 avg_tb_size=376 qemu: flush code_size=50782632 nb_tbs=90681 avg_tb_size=374 qemu: flush code_size=39848888 nb_tbs=71433 avg_tb_size=372 qemu: flush code_size=64708840 nb_tbs=119052 avg_tb_size=359 qemu: flush code_size=49830008 nb_tbs=90992 avg_tb_size=362 qemu: flush code_size=68372408 nb_tbs=123442 avg_tb_size=368 qemu: flush code_size=33555560 nb_tbs=59514 avg_tb_size=378 qemu: flush code_size=44748344 nb_tbs=80974 avg_tb_size=367 qemu: flush code_size=37104248 nb_tbs=67609 avg_tb_size=364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Backports commit e8feb96fcc6c16eab8923332e86ff4ef0e2ac276 from qemu
2018-03-14 15:14:31 +00:00
'tcg_region_init',
'tcg_region_reset_all',
tcg: enable multiple TCG contexts in softmmu This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that targets do not need any conversion: targets initialize a TCGContext (e.g. defining TCG globals), and after this initialization has finished, the context is cloned by the vCPU threads, each of them keeping a separate copy. TCG threads claim one entry in tcg_ctxs[] by atomically increasing n_tcg_ctxs. Do not be too annoyed by the subsequent atomic_read's of that variable and tcg_ctxs; they are there just to play nice with analysis tools such as thread sanitizer. Note that we do not allocate an array of contexts (we allocate an array of pointers instead) because when tcg_context_init is called, we do not know yet how many contexts we'll use since the bool behind qemu_tcg_mttcg_enabled() isn't set yet. Previous patches folded some TCG globals into TCGContext. The non-const globals remaining are only set at init time, i.e. before the TCG threads are spawned. Here is a list of these set-at-init-time globals under tcg/: Only written by tcg_context_init: - indirect_reg_alloc_order - tcg_op_defs Only written by tcg_target_init (called from tcg_context_init): - tcg_target_available_regs - tcg_target_call_clobber_regs - arm: arm_arch, use_idiv_instructions - i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt, have_movbe, have_popcnt - mips: use_movnz_instructions, use_mips32_instructions, use_mips32r2_instructions, got_sigill (tcg_target_detect_isa) - ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr - s390: tb_ret_addr, s390_facilities - sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines), use_vis3_instructions Only written by tcg_prologue_init: - 'struct jit_code_entry one_entry' - aarch64: tb_ret_addr - arm: tb_ret_addr - i386: tb_ret_addr, guest_base_flags - ia64: tb_ret_addr - mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr Backports commit 3468b59e18b179bc63c7ce934de912dfa9596122 from qemu
2018-03-14 16:55:59 +00:00
'tcg_register_thread',
import
2015-08-21 07:04:50 +00:00
'tcg_set_frame',
'tcg_set_nop',
'tcg_swap_cond',
'tcg_target_call_iarg_regs',
'tcg_target_call_oarg_regs',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_target_callee_save_regs',
import
2015-08-21 07:04:50 +00:00
'tcg_target_const_match',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tcg_target_deposit_valid',
import
2015-08-21 07:04:50 +00:00
'tcg_target_init',
'tcg_target_qemu_prologue',
'tcg_target_reg_alloc_order',
tcg: allocate TB structs before the corresponding translated code Allocating an arbitrarily-sized array of tbs results in either (a) a lot of memory wasted or (b) unnecessary flushes of the code cache when we run out of TB structs in the array. An obvious solution would be to just malloc a TB struct when needed, and keep the TB array as an array of pointers (recall that tb_find_pc() needs the TB array to run in O(log n)). Perhaps a better solution, which is implemented in this patch, is to allocate TB's right before the translated code they describe. This results in some memory waste due to padding to have code and TBs in separate cache lines--for instance, I measured 4.7% of padding in the used portion of code_gen_buffer when booting aarch64 Linux on a host with 64-byte cache lines. However, it can allow for optimizations in some host architectures, since TCG backends could safely assume that the TB and the corresponding translated code are very close to each other in memory. See this message by rth for a detailed explanation: https://lists.gnu.org/archive/html/qemu-devel/2017-03/msg05172.html Subject: Re: GSoC 2017 Proposal: TCG performance enhancements Backports commit 6e3b2bfd6af488a896f7936e99ef160f8f37e6f2 from qemu
2018-03-03 22:01:28 +00:00
'tcg_tb_alloc',
import
2015-08-21 07:04:50 +00:00
'tcg_temp_alloc',
'tcg_temp_free_i32',
'tcg_temp_free_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_temp_free_vec',
import
2015-08-21 07:04:50 +00:00
'tcg_temp_free_internal',
'tcg_temp_local_new_i32',
'tcg_temp_local_new_i64',
'tcg_temp_new_i32',
'tcg_temp_new_i64',
'tcg_temp_new_internal',
'tcg_temp_new_internal_i32',
'tcg_temp_new_internal_i64',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'tcg_temp_new_vec',
'tcg_temp_new_vec_matching',
import
2015-08-21 07:04:50 +00:00
'tdb_hash',
'teecr_write',
'teehbr_access',
'temp_allocate_frame',
'temp_dead',
'temp_save',
'temp_sync',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'temps_are_copies',
import
2015-08-21 07:04:50 +00:00
'tgen_arithi',
'tgen_arithr',
'thumb2_logic_op',
'ti925t_initfn',
'tlb_add_large_page',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tlb_fill',
'tlb_flush',
cputlb: Add functions for flushing TLB for a single MMU index Guest CPU TLB maintenance operations may be sufficiently specialized to only need to flush TLB entries corresponding to a particular MMU index. Implement cputlb functions for this, to avoid the inefficiency of flushing TLB entries which we don't need to. Backports commit d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d from qemu
2018-02-15 14:34:07 +00:00
'tlb_flush_by_mmuidx',
import
2015-08-21 07:04:50 +00:00
'tlb_flush_entry',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tlb_flush_page',
cputlb: Add functions for flushing TLB for a single MMU index Guest CPU TLB maintenance operations may be sufficiently specialized to only need to flush TLB entries corresponding to a particular MMU index. Implement cputlb functions for this, to avoid the inefficiency of flushing TLB entries which we don't need to. Backports commit d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d from qemu
2018-02-15 14:34:07 +00:00
'tlb_flush_page_by_mmuidx',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tlb_is_dirty_ram',
'tlb_reset_dirty',
'tlb_reset_dirty_range',
'tlb_set_dirty',
'tlb_set_page',
'tlb_set_page_with_attrs',
'tlb_vaddr_to_host',
import
2015-08-21 07:04:50 +00:00
'tlbi_aa64_asid_is_write',
'tlbi_aa64_asid_write',
'tlbi_aa64_va_is_write',
'tlbi_aa64_va_write',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tlbi_aa64_vaa_is_write',
'tlbi_aa64_vaa_write',
import
2015-08-21 07:04:50 +00:00
'tlbiall_is_write',
'tlbiall_write',
'tlbiasid_is_write',
'tlbiasid_write',
'tlbimva_is_write',
'tlbimva_write',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'tlbimvaa_is_write',
'tlbimvaa_write',
'to_qiv',
'to_qov',
import
2015-08-21 07:04:50 +00:00
'token_get_type',
'token_get_value',
'token_is_escape',
'token_is_keyword',
'token_is_operator',
'tokens_append_from_iter',
'tosa_init',
Use DEFINE_MACHINE() to register all machines Convert all machines to use DEFINE_MACHINE() instead of QEMUMachine automatically using a script. Backports commit e264d29de28c5b0be3d063307ce9fb613b427cc3 from qemu
2018-03-11 18:49:09 +00:00
'tosa_machine_init_register_types',
tcg: Add generic translation framework Backports commit bb2e0039dc07177f928f9fe24758967da02d60a2 from qemu
2018-03-04 19:13:08 +00:00
'translator_loop',
'translator_loop_temp_check',
import
2015-08-21 07:04:50 +00:00
'tswap32',
'tswap64',
'type_class_get_size',
'type_get_by_name',
'type_get_parent',
'type_has_parent',
'type_initialize',
'type_initialize_interface',
'type_is_ancestor',
'type_new',
'type_object_get_size',
'type_register_internal',
'type_table_add',
'type_table_get',
'type_table_lookup',
fpu/softfloat: re-factor int/uint to float These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 17:10:00 +00:00
'uint16_to_float16',
import
2015-08-21 07:04:50 +00:00
'uint16_to_float32',
'uint16_to_float64',
fpu/softfloat: re-factor int/uint to float These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 17:10:00 +00:00
'uint32_to_float16',
import
2015-08-21 07:04:50 +00:00
'uint32_to_float32',
'uint32_to_float64',
'uint64_to_float128',
fpu/softfloat: re-factor int/uint to float These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 17:10:00 +00:00
'uint64_to_float16',
import
2015-08-21 07:04:50 +00:00
'uint64_to_float32',
'uint64_to_float64',
'unassigned_io_ops',
'unassigned_io_read',
'unassigned_io_write',
'unassigned_mem_accepts',
'unassigned_mem_ops',
'unassigned_mem_read',
'unassigned_mem_write',
memory: Share special empty FlatView This shares an cached empty FlatView among address spaces. The empty FV is used every time when a root MR renders into a FV without memory sections which happens when MR or its children are not enabled or zero-sized. The empty_view is not NULL to keep the rest of memory API intact; it also has a dispatch tree for the same reason. On POWER8 with 255 CPUs, 255 virtio-net, 40 PCI bridges guest this halves the amount of FlatView's in use (557 -> 260) and dispatch tables (~800000 -> ~370000). In an unrelated experiment with 112 non-virtio devices on x86 ("-M pc"), only 4 FlatViews are alive, and about ~2000 are created at startup. Backports commit 092aa2fc65b7a35121616aad8f39d47b8f921618 from qemu
2018-03-12 02:23:21 +00:00
'unicorn_free_empty_flat_view',
import
2015-08-21 07:04:50 +00:00
'update_spsel',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'use_idiv_instructions_rt',
import
2015-08-21 07:04:50 +00:00
'v6_cp_reginfo',
'v6k_cp_reginfo',
'v7_cp_reginfo',
'v7m_pop',
'v7m_push',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'v7mp_cp_reginfo',
import
2015-08-21 07:04:50 +00:00
'v8_cp_reginfo',
'v8_el2_cp_reginfo',
'v8_el3_cp_reginfo',
'v8_el3_no_el2_cp_reginfo',
'vapa_cp_reginfo',
'vbar_write',
tcg: Add types and basic operations for host vectors Nothing uses or enables them yet. Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 16:49:50 +00:00
'vec_gen_2',
'vec_gen_3',
'vec_gen_4',
import
2015-08-21 07:04:50 +00:00
'vfp_exceptbits_from_host',
'vfp_exceptbits_to_host',
'vfp_get_fpcr',
'vfp_get_fpscr',
'vfp_get_fpsr',
'vfp_reg_offset',
'vfp_set_fpcr',
'vfp_set_fpscr',
'vfp_set_fpsr',
'visit_end_implicit_struct',
'visit_end_list',
'visit_end_struct',
'visit_end_union',
'visit_get_next_type',
'visit_next_list',
'visit_optional',
'visit_start_implicit_struct',
'visit_start_list',
'visit_start_struct',
'visit_start_union',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'vm_start',
import
2015-08-21 07:04:50 +00:00
'vmsa_cp_reginfo',
'vmsa_tcr_el1_write',
'vmsa_ttbcr_raw_write',
'vmsa_ttbcr_reset',
'vmsa_ttbcr_write',
'vmsa_ttbr_write',
'write_cpustate_to_list',
'write_list_to_cpustate',
'write_raw_cp_reg',
target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode In the v7M architecture, there is an invariant that if the CPU is in Handler mode then the CONTROL.SPSEL bit cannot be nonzero. This in turn means that the current stack pointer is always indicated by CONTROL.SPSEL, even though Handler mode always uses the Main stack pointer. In v8M, this invariant is removed, and CONTROL.SPSEL may now be nonzero in Handler mode (though Handler mode still always uses the Main stack pointer). In preparation for this change, change how we handle this bit: rename switch_v7m_sp() to the now more accurate write_v7m_control_spsel(), and make it check both the handler mode state and the SPSEL bit. Note that this implicitly changes the point at which we switch active SP on exception exit from before we pop the exception frame to after it. Backports commit de2db7ec894f11931932ca78cd14a8d2b1389d5b from qemu
2018-03-05 06:29:51 +00:00
'write_v7m_exception',
target-i386: Use correct memory attributes for memory accesses These include page table walks, SVM accesses and SMM state save accesses. The bulk of the patch is obtained with sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/' Backports commit b216aa6c0fcbaa8ff4128969c14594896a5485a4 from qemu
2018-02-13 16:52:25 +00:00
'x86_ldl_phys',
'x86_ldq_phys',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'x86_ldub_phys',
'x86_lduw_phys',
import
2015-08-21 07:04:50 +00:00
'x86_op_defs',
target-i386: Use correct memory attributes for memory accesses These include page table walks, SVM accesses and SMM state save accesses. The bulk of the patch is obtained with sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/' Backports commit b216aa6c0fcbaa8ff4128969c14594896a5485a4 from qemu
2018-02-13 16:52:25 +00:00
'x86_stb_phys',
'x86_stl_phys',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'x86_stl_phys_notdirty',
target-i386: Use correct memory attributes for memory accesses These include page table walks, SVM accesses and SMM state save accesses. The bulk of the patch is obtained with sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/' Backports commit b216aa6c0fcbaa8ff4128969c14594896a5485a4 from qemu
2018-02-13 16:52:25 +00:00
'x86_stq_phys',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'x86_stw_phys',
import
2015-08-21 07:04:50 +00:00
'xpsr_read',
'xpsr_write',
target-arm: add async excp target_el function Adds a dedicated function and a lookup table for determining the target exception level of IRQ and FIQ exceptions. The lookup table is taken from the ARMv7 and ARMv8 specification exception routing tables. Backports commit 0eeb17d618361a0f4faddc160e33598b23da6dd5 from qemu
2018-02-11 22:42:00 +00:00
'xscale_cp_reginfo',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'xscale_cpar_write',
import
2015-08-21 07:04:50 +00:00
)
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 14:25:35 +00:00
arm_symbols = (
target/arm: [tcg] Port to generic translation framework Backports commit 2316922420da6fd0d1ffb5557d0cdcc5958bcf44 from qemu
2018-03-05 01:11:49 +00:00
'aarch64_translator_ops',
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 14:25:35 +00:00
'ARM_REGS_STORAGE_SIZE',
target-arm: Infrastucture changes to enable handling of tagged address loading into PC When capturing the current CPU state for the TB, extract the TBI0 and TBI1 values from the correct TCR for the current EL and then add them to the TB flags field. Then, at the start of code generation for the block, copy the TBI fields into the DisasContext structure. Backports commit 86fb3fa4ed5873b021a362ea26a021f4aeab1bb4 from qemu
2018-02-26 12:58:04 +00:00
'arm_regime_tbi0',
'arm_regime_tbi1',
header_gen: alphabetize ARM symbols
2018-02-26 00:00:31 +00:00
'arm_register_el_change_hook',
ARM: Factor out ARM on/off PSCI control functions Split ARM on/off function from PSCI support code. This will allow to reuse these functions in other code. Backports commit 825482adde1f971cbddf27e15fb4453ab3fae994 from qemu
2018-03-02 04:11:30 +00:00
'arm_reset_cpu',
'arm_set_cpu_off',
'arm_set_cpu_on',
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 14:25:35 +00:00
)
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
aarch64_symbols = (
'ARM64_REGS_STORAGE_SIZE',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'aarch64_cpu_do_interrupt',
'aarch64_cpu_register_types',
target/arm: [tcg] Port to generic translation framework Backports commit 2316922420da6fd0d1ffb5557d0cdcc5958bcf44 from qemu
2018-03-05 01:11:49 +00:00
'aarch64_translator_ops',
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
'arm64_reg_read',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'arm64_reg_reset',
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
'arm64_reg_write',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'arm64_release',
target-arm: Infrastucture changes to enable handling of tagged address loading into PC When capturing the current CPU state for the TB, extract the TBI0 and TBI1 values from the correct TCR for the current EL and then add them to the TB flags field. Then, at the start of code generation for the block, copy the TBI fields into the DisasContext structure. Backports commit 86fb3fa4ed5873b021a362ea26a021f4aeab1bb4 from qemu
2018-02-26 12:58:04 +00:00
'arm_regime_tbi0',
'arm_regime_tbi1',
target-arm: Provide hook to tell GICv3 about changes of security state The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Backports commit bd7d00fc50c9960876dd194ebf0c88889b53e765 from qemu
2018-02-25 00:07:35 +00:00
'arm_register_el_change_hook',
ARM: Factor out ARM on/off PSCI control functions Split ARM on/off function from PSCI support code. This will allow to reuse these functions in other code. Backports commit 825482adde1f971cbddf27e15fb4453ab3fae994 from qemu
2018-03-02 04:11:30 +00:00
'arm_reset_cpu',
'arm_set_cpu_off',
'arm_set_cpu_on',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'gen_a64_set_pc_im',
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu
2018-03-08 17:59:06 +00:00
'helper_advsimd_acge_f16',
'helper_advsimd_acgt_f16',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_add2h',
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 17:54:44 +00:00
'helper_advsimd_addh',
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu
2018-03-08 17:59:06 +00:00
'helper_advsimd_ceq_f16',
'helper_advsimd_cge_f16',
'helper_advsimd_cgt_f16',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_div2h',
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 17:54:44 +00:00
'helper_advsimd_divh',
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 This covers all the floating point convert operations. Backports commit 2df581304193d70eaf0d22cf4cb4613f74b6e59b from qemu
2018-03-08 23:24:36 +00:00
'helper_advsimd_f16tosinth',
'helper_advsimd_f16touinth',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_max2h',
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 17:49:26 +00:00
'helper_advsimd_maxh',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_maxnum2h',
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 17:49:26 +00:00
'helper_advsimd_maxnumh',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_min2h',
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 17:49:26 +00:00
'helper_advsimd_minh',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_minnum2h',
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 17:49:26 +00:00
'helper_advsimd_minnumh',
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0
2018-03-08 20:36:50 +00:00
'helper_advsimd_muladdh',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_muladd2h',
'helper_advsimd_mul2h',
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 17:54:44 +00:00
'helper_advsimd_mulh',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_mulx2h',
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0
2018-03-08 20:36:50 +00:00
'helper_advsimd_mulxh',
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 This adds the full range of half-precision floating point to integral instructions. Backports commit 6109aea2d954891027acba64a13f1f1c7463cfac from qemu
2018-03-08 23:20:37 +00:00
'helper_advsimd_rinth',
'helper_advsimd_rinth_exact',
arm/translate-a64: add FP16 x2 ops for simd_indexed A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 23:06:25 +00:00
'helper_advsimd_sub2h',
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 17:54:44 +00:00
'helper_advsimd_subh',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'helper_crc32_64',
'helper_crc32c_64',
'helper_fcvtx_f64_to_f32',
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 We go with the localised helper. Backports commit 986950283837f697b35782b9ac3bc99fca614640 from qemu
2018-03-09 00:15:05 +00:00
'helper_frecpx_f16',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'helper_frecpx_f32',
'helper_frecpx_f64',
'helper_neon_addlp_s16',
'helper_neon_addlp_s8',
'helper_neon_addlp_u16',
'helper_neon_addlp_u8',
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
'helper_neon_ceq_f64',
'helper_neon_cge_f64',
'helper_neon_cgt_f64',
target-arm: emulate aarch64's LL/SC using cmpxchg helpers Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable alternative. The appended emulates LL/SC pairs in aarch64 with cmpxchg helpers. This works in both user and system mode. In usermode, it avoids pausing all other CPUs to perform the LL/SC pair. The subsequent performance and scalability improvement is significant, as the plots below show. They plot the throughput of atomic_add-bench compiled for ARM and executed on a 64-core x86 machine. Hi-res plots: http://imgur.com/a/JVc8Y atomic_add-bench: 1000000 ops/thread, [0,1] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ || | 14 ++ ++ | | | 12 ++| ++ | | | 10 ++++ ++ 8 ++E ++ |+++ | 6 ++ | ++ | | | 4 ++ | ++ | | | 2 +H++E+--- ++ + | +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,2] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ | | | 14 ++E ++ | | | 12 ++| ++ |+++ | 10 ++ | ++ 8 ++ | ++ | | | 6 ++ | ++ | | | 4 ++ | ++ | +E+--- | 2 +H+ +E+-----+++ +++ +++ ---+E+-----+E+------+++ +++ + +E+---+--+E+----++E+------+E+--- ++++ +++ + +E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,128] range 70 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 60 ++master +-H--+ +++ ---+E+-----+E+------+E+ | +E+------E-------+E+--- | | --- +++ | 50 ++ +++--- ++ | -+E+ | 40 ++ +++---- ++ | E- | | --| | 30 ++ -- +++ ++ | +E+ | 20 ++E+ ++ |E+ | | | 10 ++ ++ + + + + + + + | 0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,1024] range 160 ++---------+---------+----------+---------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 140 ++master +-H--+ +++ +++ | -+E+-----+E+-------E| 120 ++ +++ ---- +++ | +++ ----E-- | 100 ++ --E--- +++ ++ | +++ ---- +++ | 80 ++ --E-- ++ | ---- +++ | | -+E+ | 60 ++ ---- +++ ++ | +E+- | 40 ++ -- ++ | +E+ | 20 +EE+ ++ +++ + + + + + + | 0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads Backports commit 1dd089d0eec060dcd8478735114d98421d414805 from qemu
2018-02-28 05:13:19 +00:00
'helper_paired_cmpxchg64_be',
target/arm: check CF_PARALLEL instead of parallel_cpus Thereby decoupling the resulting translated code from the current state of the system. Backports commit 2399d4e7cec22ecf1c51062d2ebfd45220dbaace from qemu
2018-03-13 19:00:48 +00:00
'helper_paired_cmpxchg64_be_parallel',
target-arm: emulate aarch64's LL/SC using cmpxchg helpers Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable alternative. The appended emulates LL/SC pairs in aarch64 with cmpxchg helpers. This works in both user and system mode. In usermode, it avoids pausing all other CPUs to perform the LL/SC pair. The subsequent performance and scalability improvement is significant, as the plots below show. They plot the throughput of atomic_add-bench compiled for ARM and executed on a 64-core x86 machine. Hi-res plots: http://imgur.com/a/JVc8Y atomic_add-bench: 1000000 ops/thread, [0,1] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ || | 14 ++ ++ | | | 12 ++| ++ | | | 10 ++++ ++ 8 ++E ++ |+++ | 6 ++ | ++ | | | 4 ++ | ++ | | | 2 +H++E+--- ++ + | +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,2] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ | | | 14 ++E ++ | | | 12 ++| ++ |+++ | 10 ++ | ++ 8 ++ | ++ | | | 6 ++ | ++ | | | 4 ++ | ++ | +E+--- | 2 +H+ +E+-----+++ +++ +++ ---+E+-----+E+------+++ +++ + +E+---+--+E+----++E+------+E+--- ++++ +++ + +E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,128] range 70 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 60 ++master +-H--+ +++ ---+E+-----+E+------+E+ | +E+------E-------+E+--- | | --- +++ | 50 ++ +++--- ++ | -+E+ | 40 ++ +++---- ++ | E- | | --| | 30 ++ -- +++ ++ | +E+ | 20 ++E+ ++ |E+ | | | 10 ++ ++ + + + + + + + | 0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,1024] range 160 ++---------+---------+----------+---------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 140 ++master +-H--+ +++ +++ | -+E+-----+E+-------E| 120 ++ +++ ---- +++ | +++ ----E-- | 100 ++ --E--- +++ ++ | +++ ---- +++ | 80 ++ --E-- ++ | ---- +++ | | -+E+ | 60 ++ ---- +++ ++ | +E+- | 40 ++ -- ++ | +E+ | 20 +EE+ ++ +++ + + + + + + | 0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads Backports commit 1dd089d0eec060dcd8478735114d98421d414805 from qemu
2018-02-28 05:13:19 +00:00
'helper_paired_cmpxchg64_le',
target/arm: check CF_PARALLEL instead of parallel_cpus Thereby decoupling the resulting translated code from the current state of the system. Backports commit 2399d4e7cec22ecf1c51062d2ebfd45220dbaace from qemu
2018-03-13 19:00:48 +00:00
'helper_paired_cmpxchg64_le_parallel',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'helper_rbit64',
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Backports commit 026e2d6ef74000afb9049f46add4b94f594c8fb3 from qemu
2018-03-08 20:44:29 +00:00
'helper_recpsf_f16',
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
'helper_recpsf_f32',
'helper_recpsf_f64',
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Backports commit 026e2d6ef74000afb9049f46add4b94f594c8fb3 from qemu
2018-03-08 20:44:29 +00:00
'helper_rsqrtsf_f16',
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
'helper_rsqrtsf_f32',
'helper_rsqrtsf_f64',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'helper_sdiv64',
'helper_simd_tbl',
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 Backports commit b96a54c7e5576bd35b7d00d37b7929d2892d8cac from qemu
2018-03-09 02:54:26 +00:00
'helper_sqrt_f16',
header_gen: alphabetize aarch64 symbols
2018-02-25 23:59:29 +00:00
'helper_udiv64',
'helper_vfp_cmpd_a64',
'helper_vfp_cmped_a64',
'helper_vfp_cmpes_a64',
'helper_vfp_cmps_a64',
'helper_vfp_mulxd',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'helper_vfp_mulxs'
)
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
import
2015-08-21 07:04:50 +00:00
mips_symbols = (
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'MIPS64_REGS_STORAGE_SIZE',
'MIPS_REGS_STORAGE_SIZE',
import
2015-08-21 07:04:50 +00:00
'cpu_mips_exec',
'cpu_mips_get_count',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'cpu_mips_get_random',
'cpu_mips_kseg0_to_phys',
'cpu_mips_kvm_um_phys_to_kseg0',
'cpu_mips_phys_to_kseg0',
mips: split cpu_mips_realize_env() out of cpu_mips_init() so it can be used in mips_cpu_realizefn() in the next commit Backports commit 27e38392ca07f97edfb2257b6a1394a04d84e8d5 from qemu
2018-03-05 05:27:22 +00:00
'cpu_mips_realize_env',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'cpu_mips_start_count',
'cpu_mips_stop_count',
mips: move CP0 functions out of cpu.h These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Backports commit e6623d88f44aae9e9c78276c0cb7bd352283d50a from qemu
2018-02-24 06:57:26 +00:00
'cpu_mips_store_cause',
import
2015-08-21 07:04:50 +00:00
'cpu_mips_store_compare',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'cpu_mips_store_count',
mips: move CP0 functions out of cpu.h These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Backports commit e6623d88f44aae9e9c78276c0cb7bd352283d50a from qemu
2018-02-24 06:57:26 +00:00
'cpu_mips_store_status',
'cpu_mips_tlb_flush',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'cpu_mips_translate_address',
'cpu_rddsp',
'cpu_set_exception_base',
import
2015-08-21 07:04:50 +00:00
'cpu_state_reset',
target-mips: Provide function to test if a CPU supports an ISA Provide a new cpu_supports_isa function which allows callers to determine whether a CPU supports one of the ISA_ flags, by testing whether the associated struct mips_def_t sets the ISA flags in its insn_flags field. An example use of this is to allow boards which generate bootloader code to determine the properties of the CPU that will be used, for example whether the CPU is 64 bit or which architecture revision it implements. Backports commit bed9e5ceb158c886d548fe59675a6eba18baeaeb from qemu
2018-03-02 13:19:46 +00:00
'cpu_supports_isa',
target/mips/translate: Perform comparison pass with qemu Keeps code and formatting in sync
2018-03-12 19:32:55 +00:00
'cpu_supports_cps_smp',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'cpu_wrdsp',
qemu-common: push cpu.h inclusion out of qemu-common.h Backports commit 33c11879fd422b759483ed25fef133ea900ea8d7 from qemu
2018-02-24 06:23:15 +00:00
'do_raise_exception_err',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'exception_resume_pc',
'fixed_mmu_map_address',
softfloat: Implement run-time-configurable meaning of signaling NaN bit This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Backports commit af39bc8c49224771ec0d38f1b693ea78e221d7bc from qemu
2018-02-25 00:43:05 +00:00
'float_class_d',
'float_class_s',
'gen_helper_float_class_d',
'gen_helper_float_class_s',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_absq_s_ob',
import
2015-08-21 07:04:50 +00:00
'helper_absq_s_ph',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_absq_s_pw',
import
2015-08-21 07:04:50 +00:00
'helper_absq_s_qb',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_absq_s_qh',
import
2015-08-21 07:04:50 +00:00
'helper_absq_s_w',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_addq_ph',
'helper_addq_pw',
'helper_addq_qh',
'helper_addq_s_ph',
'helper_addq_s_pw',
'helper_addq_s_qh',
'helper_addq_s_w',
import
2015-08-21 07:04:50 +00:00
'helper_addqh_ph',
'helper_addqh_r_ph',
'helper_addqh_r_w',
'helper_addqh_w',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_addsc',
'helper_addu_ob',
import
2015-08-21 07:04:50 +00:00
'helper_addu_ph',
'helper_addu_qb',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_addu_qh',
'helper_addu_s_ob',
import
2015-08-21 07:04:50 +00:00
'helper_addu_s_ph',
'helper_addu_s_qb',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_addu_s_qh',
'helper_adduh_ob',
'helper_adduh_qb',
'helper_adduh_r_ob',
'helper_adduh_r_qb',
import
2015-08-21 07:04:50 +00:00
'helper_addwc',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_biadd',
'helper_bitrev',
'helper_bitswap',
target-mips: make ITC Configuration Tags accessible to the CPU Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Backports commit 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776 from qemu
2018-03-04 05:25:17 +00:00
'helper_cache',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_cfc1',
'helper_cmp_d_eq',
'helper_cmp_d_f',
'helper_cmp_d_le',
'helper_cmp_d_lt',
'helper_cmp_d_nge',
'helper_cmp_d_ngl',
'helper_cmp_d_ngle',
'helper_cmp_d_ngt',
'helper_cmp_d_ole',
'helper_cmp_d_olt',
'helper_cmp_d_seq',
'helper_cmp_d_sf',
'helper_cmp_d_ueq',
'helper_cmp_d_ule',
'helper_cmp_d_ult',
'helper_cmp_d_un',
'helper_cmp_eq_ph',
'helper_cmp_eq_pw',
'helper_cmp_eq_qh',
'helper_cmp_le_ph',
'helper_cmp_le_pw',
'helper_cmp_le_qh',
'helper_cmp_lt_ph',
'helper_cmp_lt_pw',
'helper_cmp_lt_qh',
'helper_cmp_ps_eq',
'helper_cmp_ps_f',
'helper_cmp_ps_le',
'helper_cmp_ps_lt',
'helper_cmp_ps_nge',
'helper_cmp_ps_ngl',
'helper_cmp_ps_ngle',
'helper_cmp_ps_ngt',
'helper_cmp_ps_ole',
'helper_cmp_ps_olt',
'helper_cmp_ps_seq',
'helper_cmp_ps_sf',
'helper_cmp_ps_ueq',
'helper_cmp_ps_ule',
'helper_cmp_ps_ult',
'helper_cmp_ps_un',
'helper_cmp_s_eq',
'helper_cmp_s_f',
'helper_cmp_s_le',
'helper_cmp_s_lt',
'helper_cmp_s_nge',
'helper_cmp_s_ngl',
'helper_cmp_s_ngle',
'helper_cmp_s_ngt',
'helper_cmp_s_ole',
'helper_cmp_s_olt',
'helper_cmp_s_seq',
'helper_cmp_s_sf',
'helper_cmp_s_ueq',
'helper_cmp_s_ule',
'helper_cmp_s_ult',
'helper_cmp_s_un',
'helper_cmpabs_d_eq',
'helper_cmpabs_d_f',
'helper_cmpabs_d_le',
'helper_cmpabs_d_lt',
'helper_cmpabs_d_nge',
'helper_cmpabs_d_ngl',
'helper_cmpabs_d_ngle',
'helper_cmpabs_d_ngt',
'helper_cmpabs_d_ole',
'helper_cmpabs_d_olt',
'helper_cmpabs_d_seq',
'helper_cmpabs_d_sf',
'helper_cmpabs_d_ueq',
'helper_cmpabs_d_ule',
'helper_cmpabs_d_ult',
'helper_cmpabs_d_un',
'helper_cmpabs_ps_eq',
'helper_cmpabs_ps_f',
'helper_cmpabs_ps_le',
'helper_cmpabs_ps_lt',
'helper_cmpabs_ps_nge',
'helper_cmpabs_ps_ngl',
'helper_cmpabs_ps_ngle',
'helper_cmpabs_ps_ngt',
'helper_cmpabs_ps_ole',
'helper_cmpabs_ps_olt',
'helper_cmpabs_ps_seq',
'helper_cmpabs_ps_sf',
'helper_cmpabs_ps_ueq',
'helper_cmpabs_ps_ule',
'helper_cmpabs_ps_ult',
'helper_cmpabs_ps_un',
'helper_cmpabs_s_eq',
'helper_cmpabs_s_f',
'helper_cmpabs_s_le',
'helper_cmpabs_s_lt',
'helper_cmpabs_s_nge',
'helper_cmpabs_s_ngl',
'helper_cmpabs_s_ngle',
'helper_cmpabs_s_ngt',
'helper_cmpabs_s_ole',
'helper_cmpabs_s_olt',
'helper_cmpabs_s_seq',
'helper_cmpabs_s_sf',
'helper_cmpabs_s_ueq',
'helper_cmpabs_s_ule',
'helper_cmpabs_s_ult',
'helper_cmpabs_s_un',
'helper_cmpgdu_eq_ob',
'helper_cmpgdu_le_ob',
'helper_cmpgdu_lt_ob',
'helper_cmpgu_eq_ob',
'helper_cmpgu_eq_qb',
'helper_cmpgu_le_ob',
'helper_cmpgu_le_qb',
'helper_cmpgu_lt_ob',
'helper_cmpgu_lt_qb',
'helper_cmpu_eq_ob',
'helper_cmpu_eq_qb',
'helper_cmpu_le_ob',
'helper_cmpu_le_qb',
'helper_cmpu_lt_ob',
'helper_cmpu_lt_qb',
'helper_ctc1',
'helper_dbitswap',
'helper_deret',
'helper_dextp',
'helper_dextpdp',
'helper_dextr_l',
'helper_dextr_r_l',
'helper_dextr_r_w',
'helper_dextr_rs_l',
'helper_dextr_rs_w',
'helper_dextr_s_h',
'helper_dextr_w',
'helper_di',
'helper_dinsv',
'helper_dmadd',
'helper_dmaddu',
'helper_dmfc0_lladdr',
'helper_dmfc0_maar',
'helper_dmfc0_tccontext',
'helper_dmfc0_tchalt',
'helper_dmfc0_tcrestart',
'helper_dmfc0_tcschedule',
'helper_dmfc0_tcschefback',
'helper_dmfc0_watchlo',
'helper_dmsub',
'helper_dmsubu',
'helper_dmt',
'helper_dmtc0_entrylo0',
'helper_dmtc0_entrylo1',
'helper_dmthlip',
'helper_dpa_w_ph',
'helper_dpa_w_qh',
'helper_dpaq_s_w_ph',
'helper_dpaq_s_w_qh',
'helper_dpaq_sa_l_pw',
'helper_dpaq_sa_l_w',
'helper_dpaqx_s_w_ph',
'helper_dpaqx_sa_w_ph',
'helper_dpau_h_obl',
'helper_dpau_h_obr',
import
2015-08-21 07:04:50 +00:00
'helper_dpau_h_qbl',
'helper_dpau_h_qbr',
'helper_dpax_w_ph',
'helper_dps_w_ph',
header_gen: alphabetize MIPS symbols
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'helper_dps_w_qh',
import
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'helper_dpsq_s_w_ph',
header_gen: alphabetize MIPS symbols
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'helper_dpsq_s_w_qh',
'helper_dpsq_sa_l_pw',
'helper_dpsq_sa_l_w',
import
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'helper_dpsqx_s_w_ph',
'helper_dpsqx_sa_w_ph',
header_gen: alphabetize MIPS symbols
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'helper_dpsu_h_obl',
'helper_dpsu_h_obr',
'helper_dpsu_h_qbl',
'helper_dpsu_h_qbr',
'helper_dpsx_w_ph',
'helper_dshilo',
'helper_dvp',
'helper_dvpe',
'helper_ei',
'helper_emt',
'helper_eret',
'helper_eretnc',
'helper_evp',
'helper_evpe',
'helper_extp',
'helper_extpdp',
import
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'helper_extr_r_w',
'helper_extr_rs_w',
'helper_extr_s_h',
header_gen: alphabetize MIPS symbols
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'helper_extr_w',
'helper_float_abs_d',
'helper_float_abs_ps',
'helper_float_abs_s',
'helper_float_add_d',
'helper_float_add_ps',
'helper_float_add_s',
'helper_float_addr_ps',
'helper_float_ceil_2008_l_d',
'helper_float_ceil_2008_l_s',
'helper_float_ceil_2008_w_d',
'helper_float_ceil_2008_w_s',
'helper_float_ceil_l_d',
'helper_float_ceil_l_s',
'helper_float_ceil_w_d',
'helper_float_ceil_w_s',
'helper_float_chs_d',
'helper_float_chs_ps',
'helper_float_chs_s',
'helper_float_class_d',
'helper_float_class_s',
'helper_float_cvt_2008_l_d',
'helper_float_cvt_2008_l_s',
'helper_float_cvt_2008_w_d',
'helper_float_cvt_2008_w_s',
'helper_float_cvt_l_d',
'helper_float_cvt_l_s',
'helper_float_cvt_w_d',
'helper_float_cvt_w_s',
'helper_float_cvtd_l',
'helper_float_cvtd_s',
'helper_float_cvtd_w',
'helper_float_cvtps_pw',
'helper_float_cvtpw_ps',
'helper_float_cvts_d',
'helper_float_cvts_l',
'helper_float_cvts_pl',
'helper_float_cvts_pu',
'helper_float_cvts_w',
'helper_float_div_d',
'helper_float_div_ps',
'helper_float_div_s',
'helper_float_floor_2008_l_d',
'helper_float_floor_2008_l_s',
'helper_float_floor_2008_w_d',
'helper_float_floor_2008_w_s',
'helper_float_floor_l_d',
'helper_float_floor_l_s',
'helper_float_floor_w_d',
'helper_float_floor_w_s',
'helper_float_madd_d',
'helper_float_madd_ps',
'helper_float_madd_s',
'helper_float_maddf_d',
'helper_float_maddf_s',
'helper_float_max_d',
'helper_float_max_s',
'helper_float_maxa_d',
'helper_float_maxa_s',
'helper_float_min_d',
'helper_float_min_s',
'helper_float_mina_d',
'helper_float_mina_s',
'helper_float_msub_d',
'helper_float_msub_ps',
'helper_float_msub_s',
'helper_float_msubf_d',
'helper_float_msubf_s',
'helper_float_mul_d',
'helper_float_mul_ps',
'helper_float_mul_s',
'helper_float_mulr_ps',
'helper_float_nmadd_d',
'helper_float_nmadd_ps',
'helper_float_nmadd_s',
'helper_float_nmsub_d',
'helper_float_nmsub_ps',
'helper_float_nmsub_s',
'helper_float_recip1_d',
'helper_float_recip1_ps',
'helper_float_recip1_s',
'helper_float_recip2_d',
'helper_float_recip2_ps',
'helper_float_recip2_s',
'helper_float_recip_d',
'helper_float_recip_s',
'helper_float_rint_d',
'helper_float_rint_s',
'helper_float_round_2008_l_d',
'helper_float_round_2008_l_s',
'helper_float_round_2008_w_d',
'helper_float_round_2008_w_s',
'helper_float_round_l_d',
'helper_float_round_l_s',
'helper_float_round_w_d',
'helper_float_round_w_s',
'helper_float_rsqrt1_d',
'helper_float_rsqrt1_ps',
'helper_float_rsqrt1_s',
'helper_float_rsqrt2_d',
'helper_float_rsqrt2_ps',
'helper_float_rsqrt2_s',
'helper_float_rsqrt_d',
'helper_float_rsqrt_s',
'helper_float_sqrt_d',
'helper_float_sqrt_s',
'helper_float_sub_d',
'helper_float_sub_ps',
'helper_float_sub_s',
'helper_float_trunc_2008_l_d',
'helper_float_trunc_2008_l_s',
'helper_float_trunc_2008_w_d',
'helper_float_trunc_2008_w_s',
'helper_float_trunc_l_d',
'helper_float_trunc_l_s',
'helper_float_trunc_w_d',
'helper_float_trunc_w_s',
'helper_fork',
'helper_insv',
'helper_ldm',
'helper_ll',
'helper_lld',
'helper_lwm',
import
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'helper_macc',
'helper_macchi',
'helper_macchiu',
header_gen: alphabetize MIPS symbols
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'helper_maccu',
'helper_maq_s_l_pwl',
'helper_maq_s_l_pwr',
'helper_maq_s_w_phl',
'helper_maq_s_w_phr',
'helper_maq_s_w_qhll',
'helper_maq_s_w_qhlr',
'helper_maq_s_w_qhrl',
'helper_maq_s_w_qhrr',
'helper_maq_sa_w_phl',
'helper_maq_sa_w_phr',
'helper_maq_sa_w_qhll',
'helper_maq_sa_w_qhlr',
'helper_maq_sa_w_qhrl',
'helper_maq_sa_w_qhrr',
'helper_mfc0_count',
'helper_mfc0_debug',
'helper_mfc0_lladdr',
'helper_mfc0_maar',
import
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'helper_mfc0_mvpconf0',
'helper_mfc0_mvpconf1',
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'helper_mfc0_mvpcontrol',
import
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'helper_mfc0_random',
'helper_mfc0_tcbind',
'helper_mfc0_tccontext',
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'helper_mfc0_tchalt',
'helper_mfc0_tcrestart',
import
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'helper_mfc0_tcschedule',
'helper_mfc0_tcschefback',
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'helper_mfc0_tcstatus',
import
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'helper_mfc0_watchhi',
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'helper_mfc0_watchlo',
'helper_mfhc0_maar',
'helper_mftacx',
'helper_mftc0_cause',
'helper_mftc0_configx',
import
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'helper_mftc0_debug',
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'helper_mftc0_ebase',
'helper_mftc0_entryhi',
'helper_mftc0_epc',
'helper_mftc0_status',
'helper_mftc0_tcbind',
'helper_mftc0_tccontext',
'helper_mftc0_tchalt',
'helper_mftc0_tcrestart',
'helper_mftc0_tcschedule',
'helper_mftc0_tcschefback',
'helper_mftc0_tcstatus',
import
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'helper_mftc0_vpeconf0',
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'helper_mftc0_vpecontrol',
'helper_mftdsp',
import
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'helper_mftgpr',
'helper_mfthi',
header_gen: alphabetize MIPS symbols
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'helper_mftlo',
'helper_modsub',
'helper_msa_add_a_df',
'helper_msa_adds_a_df',
'helper_msa_adds_s_df',
'helper_msa_adds_u_df',
'helper_msa_addv_df',
'helper_msa_addvi_df',
'helper_msa_and_v',
'helper_msa_andi_b',
'helper_msa_asub_s_df',
'helper_msa_asub_u_df',
'helper_msa_ave_s_df',
'helper_msa_ave_u_df',
'helper_msa_aver_s_df',
'helper_msa_aver_u_df',
'helper_msa_bclr_df',
'helper_msa_bclri_df',
'helper_msa_binsl_df',
'helper_msa_binsli_df',
'helper_msa_binsr_df',
'helper_msa_binsri_df',
'helper_msa_bmnz_v',
'helper_msa_bmnzi_b',
'helper_msa_bmz_v',
'helper_msa_bmzi_b',
'helper_msa_bneg_df',
'helper_msa_bnegi_df',
'helper_msa_bsel_v',
'helper_msa_bseli_b',
'helper_msa_bset_df',
'helper_msa_bseti_df',
'helper_msa_ceq_df',
'helper_msa_ceqi_df',
'helper_msa_cfcmsa',
'helper_msa_cle_s_df',
'helper_msa_cle_u_df',
'helper_msa_clei_s_df',
'helper_msa_clei_u_df',
'helper_msa_clt_s_df',
'helper_msa_clt_u_df',
'helper_msa_clti_s_df',
'helper_msa_clti_u_df',
'helper_msa_copy_s_df',
'helper_msa_copy_u_df',
'helper_msa_ctcmsa',
'helper_msa_div_s_df',
'helper_msa_div_u_df',
'helper_msa_dotp_s_df',
'helper_msa_dotp_u_df',
'helper_msa_dpadd_s_df',
'helper_msa_dpadd_u_df',
'helper_msa_dpsub_s_df',
'helper_msa_dpsub_u_df',
'helper_msa_fadd_df',
'helper_msa_fcaf_df',
'helper_msa_fceq_df',
'helper_msa_fclass_df',
'helper_msa_fcle_df',
'helper_msa_fclt_df',
'helper_msa_fcne_df',
'helper_msa_fcor_df',
'helper_msa_fcueq_df',
'helper_msa_fcule_df',
'helper_msa_fcult_df',
'helper_msa_fcun_df',
'helper_msa_fcune_df',
'helper_msa_fdiv_df',
'helper_msa_fexdo_df',
'helper_msa_fexp2_df',
'helper_msa_fexupl_df',
'helper_msa_fexupr_df',
'helper_msa_ffint_s_df',
'helper_msa_ffint_u_df',
'helper_msa_ffql_df',
'helper_msa_ffqr_df',
'helper_msa_fill_df',
'helper_msa_flog2_df',
'helper_msa_fmadd_df',
'helper_msa_fmax_a_df',
'helper_msa_fmax_df',
'helper_msa_fmin_a_df',
'helper_msa_fmin_df',
'helper_msa_fmsub_df',
'helper_msa_fmul_df',
'helper_msa_frcp_df',
'helper_msa_frint_df',
'helper_msa_frsqrt_df',
'helper_msa_fsaf_df',
'helper_msa_fseq_df',
'helper_msa_fsle_df',
'helper_msa_fslt_df',
'helper_msa_fsne_df',
'helper_msa_fsor_df',
'helper_msa_fsqrt_df',
'helper_msa_fsub_df',
'helper_msa_fsueq_df',
'helper_msa_fsule_df',
'helper_msa_fsult_df',
'helper_msa_fsun_df',
'helper_msa_fsune_df',
'helper_msa_ftint_s_df',
'helper_msa_ftint_u_df',
'helper_msa_ftq_df',
'helper_msa_ftrunc_s_df',
'helper_msa_ftrunc_u_df',
'helper_msa_hadd_s_df',
'helper_msa_hadd_u_df',
'helper_msa_hsub_s_df',
'helper_msa_hsub_u_df',
'helper_msa_ilvev_df',
'helper_msa_ilvl_df',
'helper_msa_ilvod_df',
'helper_msa_ilvr_df',
'helper_msa_insert_df',
'helper_msa_insve_df',
'helper_msa_ld_df',
'helper_msa_ldi_df',
'helper_msa_madd_q_df',
'helper_msa_maddr_q_df',
'helper_msa_maddv_df',
'helper_msa_max_a_df',
'helper_msa_max_s_df',
'helper_msa_max_u_df',
'helper_msa_maxi_s_df',
'helper_msa_maxi_u_df',
'helper_msa_min_a_df',
'helper_msa_min_s_df',
'helper_msa_min_u_df',
'helper_msa_mini_s_df',
'helper_msa_mini_u_df',
'helper_msa_mod_s_df',
'helper_msa_mod_u_df',
'helper_msa_move_v',
'helper_msa_msub_q_df',
'helper_msa_msubr_q_df',
'helper_msa_msubv_df',
'helper_msa_mul_q_df',
'helper_msa_mulr_q_df',
'helper_msa_mulv_df',
'helper_msa_nloc_df',
'helper_msa_nlzc_df',
'helper_msa_nor_v',
'helper_msa_nori_b',
'helper_msa_or_v',
'helper_msa_ori_b',
'helper_msa_pckev_df',
'helper_msa_pckod_df',
'helper_msa_pcnt_df',
'helper_msa_sat_s_df',
'helper_msa_sat_u_df',
'helper_msa_shf_df',
'helper_msa_sld_df',
'helper_msa_sldi_df',
'helper_msa_sll_df',
'helper_msa_slli_df',
'helper_msa_splat_df',
'helper_msa_splati_df',
'helper_msa_sra_df',
'helper_msa_srai_df',
'helper_msa_srar_df',
'helper_msa_srari_df',
'helper_msa_srl_df',
'helper_msa_srli_df',
'helper_msa_srlr_df',
'helper_msa_srlri_df',
'helper_msa_st_df',
'helper_msa_subs_s_df',
'helper_msa_subs_u_df',
'helper_msa_subsus_u_df',
'helper_msa_subsuu_s_df',
'helper_msa_subv_df',
'helper_msa_subvi_df',
'helper_msa_vshf_df',
'helper_msa_xor_v',
'helper_msa_xori_b',
'helper_msac',
'helper_msachi',
'helper_msachiu',
'helper_msacu',
'helper_mtc0_cause',
'helper_mtc0_compare',
'helper_mtc0_config0',
'helper_mtc0_config2',
'helper_mtc0_config3',
'helper_mtc0_config4',
'helper_mtc0_config5',
'helper_mtc0_context',
'helper_mtc0_count',
'helper_mtc0_datahi',
'helper_mtc0_datalo',
'helper_mtc0_debug',
'helper_mtc0_ebase',
target-mips: make ITC Configuration Tags accessible to the CPU Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Backports commit 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776 from qemu
2018-03-04 05:25:17 +00:00
'helper_mtc0_errctl',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_mtc0_entryhi',
'helper_mtc0_entrylo0',
'helper_mtc0_entrylo1',
'helper_mtc0_framemask',
'helper_mtc0_hwrena',
'helper_mtc0_index',
'helper_mtc0_intctl',
'helper_mtc0_lladdr',
'helper_mtc0_maar',
'helper_mtc0_maari',
'helper_mtc0_mvpcontrol',
'helper_mtc0_pagegrain',
'helper_mtc0_pagemask',
'helper_mtc0_performance0',
target/mips: Add segmentation control registers The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & CP0_SegCtl2 control the behaviour and required privilege of the legacy virtual memory segments. Add them to the CP0 interface so they can be read and written when CP0_Config3.SC=1, and initialise them to describe the standard legacy layout so they can be used in future patches regardless of whether they are exposed to the guest. Backports commit cec56a733dd2c3fa81dbedbecf03922258747f7d from qemu
2018-03-04 05:49:03 +00:00
'helper_mtc0_segctl0',
'helper_mtc0_segctl1',
'helper_mtc0_segctl2',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_mtc0_srsconf0',
'helper_mtc0_srsconf1',
'helper_mtc0_srsconf2',
'helper_mtc0_srsconf3',
'helper_mtc0_srsconf4',
'helper_mtc0_srsctl',
'helper_mtc0_status',
'helper_mtc0_taghi',
'helper_mtc0_taglo',
'helper_mtc0_tcbind',
'helper_mtc0_tccontext',
'helper_mtc0_tchalt',
'helper_mtc0_tcrestart',
'helper_mtc0_tcschedule',
'helper_mtc0_tcschefback',
'helper_mtc0_tcstatus',
'helper_mtc0_vpeconf0',
'helper_mtc0_vpeconf1',
'helper_mtc0_vpecontrol',
'helper_mtc0_vpeopt',
'helper_mtc0_watchhi',
'helper_mtc0_watchlo',
'helper_mtc0_wired',
'helper_mtc0_xcontext',
'helper_mtc0_yqmask',
'helper_mthc0_maar',
'helper_mthlip',
'helper_mttacx',
'helper_mttc0_cause',
'helper_mttc0_debug',
'helper_mttc0_ebase',
'helper_mttc0_entryhi',
'helper_mttc0_status',
'helper_mttc0_tcbind',
'helper_mttc0_tccontext',
'helper_mttc0_tchalt',
'helper_mttc0_tcrestart',
'helper_mttc0_tcschedule',
'helper_mttc0_tcschefback',
'helper_mttc0_tcstatus',
'helper_mttc0_vpeconf0',
'helper_mttc0_vpecontrol',
'helper_mttdsp',
'helper_mttgpr',
'helper_mtthi',
'helper_mttlo',
'helper_mul_ph',
'helper_mul_s_ph',
'helper_muleq_s_pw_qhl',
'helper_muleq_s_pw_qhr',
'helper_muleq_s_w_phl',
'helper_muleq_s_w_phr',
'helper_muleu_s_ph_qbl',
'helper_muleu_s_ph_qbr',
'helper_muleu_s_qh_obl',
'helper_muleu_s_qh_obr',
'helper_mulhi',
'helper_mulhiu',
'helper_mulq_rs_ph',
'helper_mulq_rs_qh',
'helper_mulq_rs_w',
'helper_mulq_s_ph',
'helper_mulq_s_w',
'helper_muls',
'helper_mulsa_w_ph',
'helper_mulsaq_s_l_pw',
'helper_mulsaq_s_w_ph',
'helper_mulsaq_s_w_qh',
'helper_mulshi',
'helper_mulshiu',
'helper_mulsu',
'helper_packrl_ph',
'helper_packrl_pw',
'helper_packsshb',
'helper_packsswh',
'helper_packushb',
'helper_paddb',
'helper_paddh',
'helper_paddsb',
'helper_paddsh',
'helper_paddusb',
'helper_paddush',
'helper_paddw',
'helper_pasubub',
'helper_pavgb',
'helper_pavgh',
'helper_pcmpeqb',
'helper_pcmpeqh',
'helper_pcmpeqw',
'helper_pcmpgtb',
'helper_pcmpgth',
'helper_pcmpgtw',
'helper_pick_ob',
'helper_pick_ph',
'helper_pick_pw',
'helper_pick_qb',
'helper_pick_qh',
'helper_pmaddhw',
'helper_pmaxsh',
'helper_pmaxub',
'helper_pminsh',
'helper_pminub',
'helper_pmon',
'helper_pmovmskb',
'helper_pmulhh',
'helper_pmulhuh',
'helper_pmullh',
'helper_preceq_pw_qhl',
'helper_preceq_pw_qhla',
'helper_preceq_pw_qhr',
'helper_preceq_pw_qhra',
'helper_precequ_ph_qbl',
'helper_precequ_ph_qbla',
'helper_precequ_ph_qbr',
'helper_precequ_ph_qbra',
'helper_precequ_qh_obl',
'helper_precequ_qh_obla',
'helper_precequ_qh_obr',
'helper_precequ_qh_obra',
'helper_preceu_ph_qbl',
'helper_preceu_ph_qbla',
'helper_preceu_ph_qbr',
'helper_preceu_ph_qbra',
'helper_preceu_qh_obl',
'helper_preceu_qh_obla',
'helper_preceu_qh_obr',
'helper_preceu_qh_obra',
'helper_precr_ob_qh',
'helper_precr_qb_ph',
'helper_precr_sra_ph_w',
'helper_precr_sra_qh_pw',
'helper_precr_sra_r_ph_w',
'helper_precr_sra_r_qh_pw',
'helper_precrq_ob_qh',
'helper_precrq_ph_w',
'helper_precrq_pw_l',
'helper_precrq_qb_ph',
'helper_precrq_qh_pw',
'helper_precrq_rs_ph_w',
'helper_precrq_rs_qh_pw',
'helper_precrqu_s_ob_qh',
'helper_precrqu_s_qb_ph',
'helper_pshufh',
'helper_psllh',
'helper_psllw',
'helper_psrah',
'helper_psraw',
'helper_psrlh',
'helper_psrlw',
'helper_psubb',
'helper_psubh',
'helper_psubsb',
'helper_psubsh',
'helper_psubusb',
'helper_psubush',
'helper_psubw',
'helper_punpckhbh',
'helper_punpckhhw',
'helper_punpckhwd',
'helper_punpcklbh',
'helper_punpcklhw',
'helper_punpcklwd',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_d_af',
'helper_r6_cmp_d_eq',
'helper_r6_cmp_d_le',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_d_lt',
'helper_r6_cmp_d_ne',
'helper_r6_cmp_d_or',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_d_saf',
'helper_r6_cmp_d_seq',
'helper_r6_cmp_d_sle',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_d_slt',
'helper_r6_cmp_d_sne',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_d_sor',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_d_sueq',
'helper_r6_cmp_d_sule',
'helper_r6_cmp_d_sult',
'helper_r6_cmp_d_sun',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_d_sune',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_d_ueq',
'helper_r6_cmp_d_ule',
'helper_r6_cmp_d_ult',
'helper_r6_cmp_d_un',
'helper_r6_cmp_d_une',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_s_af',
'helper_r6_cmp_s_eq',
'helper_r6_cmp_s_le',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_s_lt',
'helper_r6_cmp_s_ne',
'helper_r6_cmp_s_or',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_s_saf',
'helper_r6_cmp_s_seq',
'helper_r6_cmp_s_sle',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_s_slt',
'helper_r6_cmp_s_sne',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_s_sor',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_s_sueq',
'helper_r6_cmp_s_sule',
'helper_r6_cmp_s_sult',
'helper_r6_cmp_s_sun',
import
2015-08-21 07:04:50 +00:00
'helper_r6_cmp_s_sune',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_r6_cmp_s_ueq',
'helper_r6_cmp_s_ule',
'helper_r6_cmp_s_ult',
'helper_r6_cmp_s_un',
'helper_r6_cmp_s_une',
'helper_raddu_l_ob',
'helper_raddu_w_qb',
'helper_raise_exception_debug',
'helper_raise_exception_err',
'helper_rddsp',
'helper_rdhwr_cc',
'helper_rdhwr_ccres',
'helper_rdhwr_cpunum',
'helper_rdhwr_performance',
'helper_rdhwr_synci_step',
'helper_rdhwr_xnp',
'helper_sc',
'helper_scd',
'helper_sdl',
'helper_sdm',
'helper_sdr',
'helper_shilo',
'helper_shll_ob',
'helper_shll_ph',
'helper_shll_pw',
'helper_shll_qb',
'helper_shll_qh',
'helper_shll_s_ph',
'helper_shll_s_pw',
'helper_shll_s_qh',
'helper_shll_s_w',
'helper_shra_ob',
'helper_shra_ph',
'helper_shra_pw',
'helper_shra_qb',
'helper_shra_qh',
'helper_shra_r_ob',
'helper_shra_r_ph',
'helper_shra_r_pw',
'helper_shra_r_qb',
'helper_shra_r_qh',
'helper_shra_r_w',
'helper_shrl_ob',
'helper_shrl_ph',
'helper_shrl_qb',
'helper_shrl_qh',
'helper_subq_ph',
import
2015-08-21 07:04:50 +00:00
'helper_subq_pw',
'helper_subq_qh',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_subq_s_ph',
import
2015-08-21 07:04:50 +00:00
'helper_subq_s_pw',
'helper_subq_s_qh',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_subq_s_w',
'helper_subqh_ph',
'helper_subqh_r_ph',
'helper_subqh_r_w',
'helper_subqh_w',
import
2015-08-21 07:04:50 +00:00
'helper_subu_ob',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_subu_ph',
'helper_subu_qb',
import
2015-08-21 07:04:50 +00:00
'helper_subu_qh',
'helper_subu_s_ob',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_subu_s_ph',
'helper_subu_s_qb',
import
2015-08-21 07:04:50 +00:00
'helper_subu_s_qh',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'helper_subuh_ob',
'helper_subuh_qb',
'helper_subuh_r_ob',
'helper_subuh_r_qb',
'helper_swl',
'helper_swm',
'helper_swr',
'helper_tlbinv',
'helper_tlbinvf',
'helper_tlbp',
'helper_tlbr',
'helper_tlbwi',
'helper_tlbwr',
'helper_wait',
'helper_wrdsp',
'helper_yield',
'ieee_ex_to_mips',
'ieee_rm',
'mips_cpu_do_interrupt',
'mips_cpu_do_unaligned_access',
'mips_cpu_exec_interrupt',
'mips_cpu_get_phys_page_debug',
'mips_cpu_handle_mmu_fault',
'mips_cpu_list',
target-mips: add exception base to MIPS CPU Replace hardcoded 0xbfc00000 with exception_base which is initialized with this default address so there is no functional change here. However, it is now exposed and consequently it will be possible to modify it from outside of the CPU. Backports commit 89777fd10fc3dd573c3b4d1b2efdd10af823c001 from qemu
2018-02-25 08:18:07 +00:00
'mips_cpu_register_types',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'mips_cpu_unassigned_access',
mips: MIPSCPU model subclasses Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Backports commit 41da212c9ce9482fcfd490170c2611470254f8dc from qemu
2018-03-05 05:38:03 +00:00
'mips_defs',
'mips_defs_number',
Use DEFINE_MACHINE() to register all machines Convert all machines to use DEFINE_MACHINE() instead of QEMUMachine automatically using a script. Backports commit e264d29de28c5b0be3d063307ce9fb613b427cc3 from qemu
2018-03-11 18:49:09 +00:00
'mips_machine_init_register_types',
import
2015-08-21 07:04:50 +00:00
'mips_reg_read',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'mips_reg_reset',
import
2015-08-21 07:04:50 +00:00
'mips_reg_write',
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 14:25:35 +00:00
'mips_release',
header_gen: alphabetize MIPS symbols
2018-02-25 23:57:39 +00:00
'mips_tcg_init',
'no_mmu_map_address',
'r4k_helper_tlbinv',
'r4k_helper_tlbinvf',
'r4k_helper_tlbp',
'r4k_helper_tlbr',
'r4k_helper_tlbwi',
'r4k_helper_tlbwr',
'r4k_invalidate_tlb',
'r4k_map_address',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'sync_c0_status',
)
import
2015-08-21 07:04:50 +00:00
sparc_symbols = (
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'cpu_cwp_dec',
'cpu_cwp_inc',
'cpu_get_psr',
'cpu_put_psr',
'cpu_put_psr_raw',
target-sparc: Introduce cpu_raise_exception_ra Several helpers call helper_raise_exception directly, which requires in turn that their callers have performed save_state. The new function allows a TCG return address to be passed in so that we can restore PC + NPC + flags data from that. This fixes a bug in the usage of helper_check_align, whose callers had not been calling save_state. It fixes another bug in which the divide helpers used GETPC at a level other than the direct callee from TCG. This allows the translator to avoid save_state prior to SAVE, RESTORE, and FLUSHW instructions. Backports commit 2f9d35fc4006122bad33f9ae3e2e51d2263e98ee from qemu
2018-02-28 17:05:48 +00:00
'cpu_raise_exception_ra',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'cpu_set_cwp',
import
2015-08-21 07:04:50 +00:00
'cpu_sparc_exec',
'cpu_sparc_init',
'cpu_sparc_set_id',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'dump_mmu',
'helper_check_align',
'helper_check_ieee_exceptions',
'helper_compute_C_icc',
'helper_compute_psr',
'helper_debug',
'helper_fabss',
import
2015-08-21 07:04:50 +00:00
'helper_faddd',
'helper_faddq',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fadds',
'helper_fcmpd',
'helper_fcmped',
'helper_fcmpeq',
'helper_fcmpes',
'helper_fcmpq',
'helper_fcmps',
import
2015-08-21 07:04:50 +00:00
'helper_fdivd',
'helper_fdivq',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fdivs',
import
2015-08-21 07:04:50 +00:00
'helper_fdmulq',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fdtoi',
'helper_fdtoq',
'helper_fdtos',
import
2015-08-21 07:04:50 +00:00
'helper_fitod',
'helper_fitoq',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fitos',
'helper_fmuld',
'helper_fmulq',
'helper_fmuls',
'helper_fnegs',
import
2015-08-21 07:04:50 +00:00
'helper_fqtod',
'helper_fqtoi',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fqtos',
'helper_fsmuld',
import
2015-08-21 07:04:50 +00:00
'helper_fsqrtd',
'helper_fsqrtq',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_fsqrts',
'helper_fstod',
'helper_fstoi',
'helper_fstoq',
'helper_fsubd',
'helper_fsubq',
'helper_fsubs',
'helper_ld_asi',
import
2015-08-21 07:04:50 +00:00
'helper_ldfsr',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_restore',
'helper_save',
import
2015-08-21 07:04:50 +00:00
'helper_sdiv_cc',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_st_asi',
import
2015-08-21 07:04:50 +00:00
'helper_taddcctv',
'helper_tsubcctv',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'helper_udiv_cc',
target-sparc: implement UA2005 GL register Backports commit cbc3a6a4cc675516328a2b0d3602355d68b6302d from qemu
2018-03-02 02:07:32 +00:00
'helper_wrgl',
import
2015-08-21 07:04:50 +00:00
'sparc_cpu_do_interrupt',
'sparc_cpu_do_unaligned_access',
'sparc_cpu_get_phys_page_debug',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'sparc_cpu_handle_mmu_fault',
'sparc_cpu_register_types',
'sparc_cpu_unassigned_access',
import
2015-08-21 07:04:50 +00:00
'sparc_reg_read',
target-sparc: Use explicit writes to cpu_fsr By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 23:40:53 +00:00
'sparc_reg_reset',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
'sparc_reg_write',
qom: Introduce CPUClass.tcg_initialize Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Backports commit 55c3ceef61fcf06fc98ddc752b7cce788ce7680b from qemu
2018-03-05 14:27:40 +00:00
'sparc_tcg_init',
header_gen: alphabetize general symbols
2018-02-26 00:07:14 +00:00
)
import
2015-08-21 07:04:50 +00:00
if __name__ == '__main__':
arch = sys.argv[1]
print("/* Autogen header for Unicorn Engine - DONOT MODIFY */")
print("#ifndef UNICORN_AUTOGEN_%s_H" %arch.upper())
print("#define UNICORN_AUTOGEN_%s_H" %arch.upper())
for s in symbols:
print("#define %s %s_%s" %(s, s, arch))
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 14:25:35 +00:00
if 'arm' in arch:
for s in arm_symbols:
print("#define %s %s_%s" %(s, s, arch))
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
if 'aarch64' in arch:
for s in aarch64_symbols:
print("#define %s %s_%s" %(s, s, arch))
import
2015-08-21 07:04:50 +00:00
if 'mips' in arch:
for s in mips_symbols:
print("#define %s %s_%s" %(s, s, arch))
if 'sparc' in arch:
for s in sparc_symbols:
print("#define %s %s_%s" %(s, s, arch))
print("#endif")
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