Commit graph

224 commits

Author SHA1 Message Date
Yongbok Kim 6e6ca4dbd4
target-mips: microMIPS32 R6 Major instructions
Add new microMIPS32 Release 6 Major opcode instructions

Backports commit ab39ee452d74855adec91056812b8e1e5166302c from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim c2550bc28a
target-mips: microMIPS32 R6 POOL32{I, C} instructions
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions

Backports commit 3b4a5489447e7ed17cc504572cf729833853e7ab from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim fe7e49dc20
target-mips: microMIPS32 R6 POOL32F instructions
Add new microMIPS32 Release 6 POOL32F instructions

Backports commit 2a24a7badeb6ad3ba72e7984f299623035d564d6 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim f816d6c637
target-mips: microMIPS32 R6 POOL32A{XF} instructions
Add new microMIPS32 Release 6 pool32a/pool32axf instructions.

Backports commit e03320958305a68f2bc6a32c87d7ed48303438f9 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim 697b234864
target-mips: microMIPS32 R6 branches and jumps
Add new microMIPS32 Release 6 branch and jump instructions.

Backports commit 65935f070aa710cf340e96ae7ee36d2c1d5c8d15 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim de26dc6854
target-mips: add microMIPS32 R6 opcode enum
Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.

Backports commit 3a1f426828cd8ffeec1a4fa8ca6ca3ed4f800edb from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim 5cca75ca10
target-mips: signal RI for removed instructions in microMIPS R6
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.

Backports commit 9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim acede6f50c
target-mips: raise RI exceptions when FIR.PS = 0
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.

Backports commit e29c962804c4dd3fabd44e703aa87eec555ed910 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim 90848d778a
target-mips: rearrange gen_compute_compact_branch
The function will be also used for microMIPS Release 6.

Backports commit 6893f07466b045c5faf314ab9e57ef3b4a6f9e49 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim 6e32aa7c3c
target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().

Backports commit 1f1b4c008e250f870719ed38fbd0bcc14322fc01 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim 14abf22311
target-mips: remove an unused argument
Remove an unused argument from decode_micromips32_opc()

Backports commit f60eeb0c5ddd8ceb8ca6b3ba032159027afab67a from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim 9750bc546f
target-mips: add microMIPS TLBINV, TLBINVF
Add microMIPS TLBINV, TLBINVF

Backports commit e60ec06357470db5a0f25901ca19b6237e6da927 from qemu
2018-02-17 15:23:10 -05:00
Yongbok Kim af0e6e9be3
target-mips: fix {RD, WR}PGPR in microMIPS
rt, rs were swapped

Backports commit 1bf5902de03732d4067c4e90171a1741d6542c45 from qemu
2018-02-17 15:23:10 -05:00
Leon Alrae 80341ab1d8
target-mips: remove identical code in different branch
Backports commit ff334767728011218c62f7476232d260cb5b28e6 from qemu
2018-02-17 15:23:10 -05:00
Leon Alrae 3d72ec65bd
target-mips: enable XPA and LPA features
Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.

Backports commit 6773f9b687e0a8ab4b638ef88d075fb233fb7669 from qemu
2018-02-13 14:14:59 -05:00
Leon Alrae aff700ae6d
target-mips: remove misleading comments in translate_init.c
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.

Backports commit 28b027d5b63c7550c7390041d6dd50948c8f55b8 from qemu
2018-02-13 14:05:25 -05:00
Leon Alrae 8743ec8b6d
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.

In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.

Backports commit 5204ea79ea739b557f47fc4db96c94edcb33a5d6 from qemu
2018-02-13 14:03:59 -05:00
Leon Alrae 59865351e0
target-mips: add CP0.PageGrain.ELPA support
CP0.PageGrain.ELPA enables support for large physical addresses. This field
is encoded as follows:
0: Large physical address support is disabled.
1: Large physical address support is enabled.

If this bit is a 1, the following changes occur to coprocessor 0 registers:
- The PFNX field of the EntryLo0 and EntryLo1 registers is writable and
concatenated with the PFN field to form the full page frame number.
- Access to optional COP0 registers with PA extension, LLAddr, TagLo is
defined.

P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if
XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode.
In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0).

env->PABITS value is constant and indicates maximum PABITS available on
a core, whereas env->PAMask is calculated from env->PABITS and is also
affected by CP0.PageGrain.ELPA.

Backports commit e117f52636d04502fab28bd3abe93347c29f39a5 from qemu
2018-02-13 13:55:53 -05:00
Leon Alrae a13d401fe8
target-mips: support Page Frame Number Extension field
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.

Backports commit cd0d45c40133ef8b409aede5ad8a99aeaf6a70fe from qemu
2018-02-13 13:49:55 -05:00
Leon Alrae 95ed79d9c2
target-mips: extend selected CP0 registers to 64-bits in MIPS32
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.

Introduce gen_move_low32() function which moves low 32 bits from 64-bit
temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
MIPS32.

Backports commit 284b731a6ae47b9ebabb9613e753c4d83cf75dd3 from qemu
2018-02-13 13:45:29 -05:00
Leon Alrae 907bb26e5f
target-mips: correct MFC0 for CP0.EntryLo in MIPS64
CP0.EntryLo bits 31:30 have to be cleared.

Backports commit b435f3f3d174721382b55bbd0c785ec50c1796a9 from qemu
2018-02-13 13:36:01 -05:00
Leon Alrae 57f57a9de4
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.

Presence of ERETNC is denoted by the Config5.LLB.

Backports commit ce9782f40ac16660ea9437bfaa2c9c34d5ed8110 from qemu
2018-02-13 13:33:37 -05:00
Yongbok Kim 922d30c448
target-mips: Misaligned memory accesses for MSA
MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all addresses for a vector store access if it is spanning
into two pages.

Separating helper functions for each data format as format is known in
translation.
To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag.
Removing save_cpu_state() call in translation because it is able to use
cpu_restore_state() on fault as GETRA() is passed.

Backports commit adc370a48fd26b92188fa4848dfb088578b1936c from qemu
2018-02-13 13:27:31 -05:00
Yongbok Kim 6d0766f246
target-mips: Misaligned memory accesses for R6
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

Backports commit be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c from qemu
2018-02-13 13:11:39 -05:00
Leon Alrae c54458b638
target-mips: add Config5.FRE support allowing Status.FR=0 emulation
This relatively small architectural feature adds the following:

FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
available.

Config5.FRE: When enabled all single-precision FP arithmetic instructions,
LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
exception.

Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.

Enable the feature in MIPS64R6-generic CPU.

Backports commit 7c979afd11b09a16634699dd6344e3ba10c9677e from qemu
2018-02-13 13:05:22 -05:00
Leon Alrae 428ffed744
target-mips: move group of functions above gen_load_fpr32()
Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().

Backports commit eab9944c7801525737626fa45cddaf00932dd2c8 from qemu
2018-02-13 12:45:27 -05:00
Leon Alrae 2d07e60f61
target-mips: save cpu state before calling MSA load and store helpers
PC needs to be saved if an exception can be generated by an helper.
This fixes a problem related to resuming the execution at unexpected address
after an exception (caused by MSA load/store instruction) has been serviced.

Backports commit 0af7a37054310384e00209e0a43efe95b7c19ef0 from qemu
2018-02-12 16:31:17 -05:00
Leon Alrae 6cd0c5d775
target-mips: fix hflags modified in delay / forbidden slot
All instructions which may change hflags terminate tb. However, this doesn't
work if such an instruction is placed in delay or forbidden slot.
gen_branch() clears MIPS_HFLAG_BMASK in ctx->hflags and then generates code
to overwrite hflags with ctx->hflags, consequently we loose any execution-time
hflags modifications. For example, in the following scenario hflag related to
Status.CU1 will not be updated:
/* Set Status.CU1 in delay slot */
mfc0 $24, $12, 0
lui $25, 0x2000
or $25, $25, $24
b check_Status_CU1
mtc0 $25, $12, 0

With this change we clear MIPS_HFLAG_BMASK in execution-time hflags if
instruction in delay or forbidden slot wants to terminate tb for some reason
(i.e. ctx->bstate != BS_NONE).

Also, die early and loudly if "unknown branch" is encountered as this should
never happen.

Backports commit a5f533909e746ca6e534b232fb42c9c6fd81b468 from qemu
2018-02-12 16:29:40 -05:00
Leon Alrae cdc72c7db1
target-mips: fix CP0.BadVAddr by stopping translation on Address Error
CP0.BadVAddr is supposed to capture the most recent virtual address that caused
the exception. Currently this does not work correctly for unaligned instruction
fetch as translation is not stopped and CP0.BadVAddr is updated with subsequent
addresses.

Backports commit 62c688693bf2f0355fc5bad5dcc59c1cd2a51f1a from qemu
2018-02-12 16:22:25 -05:00
Leon Alrae e475e68c94
target-mips: add missing MSACSR and restore fp_status and hflags
Save MSACSR state. Also remove fp_status, msa_fp_status, hflags and restore
them in post_load() from the architectural registers.
Float exception flags are not present in vmstate. Information they carry
is used only by softfloat caller who translates them into MIPS FCSR.Cause,
FCSR.Flags and then they are cleared. Therefore there is no need for saving
them in vmstate.

Backports commit 644511117e7ca9f26d633a59c202a297113a796c from qemu
2018-02-12 16:12:17 -05:00
Peter Maydell 48e9546efc
softfloat: expand out STATUS_VAR
Expand out and remove the STATUS_VAR macro.

Backports commit ff32e16e865c78fb54187723f3fd09650cd9b962 from qemu
2018-02-12 13:36:42 -05:00
Peter Maydell 20f696343b
softfloat: Expand out the STATUS_PARAM macro
Expand out STATUS_PARAM wherever it is used and delete the definition.

Backports commit e5a41ffa870ad096eb2f084447fea5dd00a51b31 from qemu
2018-02-12 13:07:53 -05:00
Leon Alrae da22a00c10
target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction
Using rs = -1 in gen_logic_imm() for microMIPS LUI instruction is dangerous
and may bite us when implementing microMIPS R6 because in R6 AUI and LUI
are distinguished by rs value. Therefore use 0 for safety.

Backports commit 5e88759a52934a32502298f2c78c6dfaa144364b from qemu
2018-02-11 17:18:08 -05:00
Leon Alrae 69974ce1dc
target-mips: use CP0EnLo_XI instead of magic number
Backports commit d3b1979d7b37c7fa6b187442e0990afa6f88fe3b from qemu
2018-02-11 17:16:31 -05:00
Leon Alrae 4d259dda9a
target-mips: ll and lld cause AdEL exception for unaligned address
Backports commit 6489dd250a4d6e86ecbb4badf82cc102afe26f33 from qemu
2018-02-11 17:14:43 -05:00
Leon Alrae c0fc9b280e
target-mips: fix detection of the end of the page during translation
The test is supposed to terminate TB if the end of the page is reached.
However, with current implementation it may never succeed for microMIPS or
mips16.

Backports commit fe2372910a09034591fd2cfc2d70cca43fccaa95 from qemu
2018-02-11 17:12:49 -05:00
Maciej W. Rozycki 6d1bc2c3c7
target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors
Backports commit 196a7958c65778d05a491309377a65c58f643a1c from qemu
2018-02-11 17:10:59 -05:00
Markus Armbruster 4ee3955e11
target-mips: Clean up switch fall through after commit fecd264
Commit fecd264 added a number of fall-throughs, but neglected to
properly document them as intentional. Commit d922445 cleaned that up
for many, but not all cases. Take care of the remaining ones.

Backports commit b6f3b233eabb4df5d65ae9fbfb3d3c8befea0de7 from qemu
2018-02-11 17:09:40 -05:00
Peter Maydell 3190a32782
target-mips: Don't use _raw load/store accessors
Use cpu_*_data instead of the direct *_raw load/store accessors.

Backports commit 15353001197c413f3ddebd51152a514dce08c458 from qemu
2018-02-11 17:06:58 -05:00
Leon Alrae 6c68869076
target-mips: remove excp_names[] from linux-user as it is unused
Backports commit d4fa5354a246a1c6cb538a5d8ebcc21206d502fb from qemu
2018-02-11 17:05:40 -05:00
Leon Alrae 30e7d6e4a4
target-mips: convert single case switch into if statement
Backports commit 00fb4a118142650e7fa3d5007b197bc11fec6ea9 from qemu
2018-02-11 17:02:09 -05:00
Maciej W. Rozycki 49cf18a8ff
target-mips: Fix DisasContext's ulri member initialization
Set DisasContext's ulri member to 0 or 1 as with other bool members.

Backports commit 66991d1103562591eba6b801049720976317fe61 from qemu
2018-02-11 17:00:31 -05:00
Lioncash bbe062a658
target-mips: Use local float status pointer across MSA macros
Reduce line wrapping throughout MSA helper macros by using a local float
status pointer rather than referring to the float status through the
environment each time. No functional change.

Backports commit 1a4d570017bf35d99340781ecb59dd3772464031 from qemu
2018-02-11 16:58:31 -05:00
Maciej W. Rozycki e97c07cdca
target-mips: Add missing calls to synchronise SoftFloat status
Add missing calls to synchronise the SoftFloat status with the CP1.FSCR:

+ for the rounding and flush-to-zero modes upon processor reset,

+ for the flush-to-zero mode on FSCR updates through the GDB stub.

Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE
macro.

Backports commit bb962386b82c1b0e9e12fdb6b9bb62106bf1f822 from qemu
2018-02-11 16:51:46 -05:00
Maciej W. Rozycki e4ce0e92b1
target-mips: Also apply the CP0.Status mask to MTTC0
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.

Backports commit 1d725ae952a14b30c84b7bc81b218b8ba77dd311 from qemu
2018-02-11 16:48:34 -05:00
Maciej W. Rozycki 29cd1237ba
target-mips: Correct 32-bit address space wrapping
Make sure the address space is unconditionally wrapped on 32-bit
processors, that is ones that do not implement at least the MIPS III
ISA.

Also make MIPS16 SAVE and RESTORE instructions use address calculation
rather than plain arithmetic operations for stack pointer manipulation
so that their semantics for stack accesses follows the architecture
specification. That in particular applies to user software run on
64-bit processors with the CP0.Status.UX bit clear where the address
space is wrapped to 32 bits.

Backports commit c48245f0c62405f27266fcf08722d8c290520418 from qemu
2018-02-11 16:47:12 -05:00
Maciej W. Rozycki 15bfd1dde7
target-mips: Tighten ISA level checks
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.

Backports commit d9224450208e0de62323b64ace91f98bc31d6e2c from qemu
2018-02-11 16:37:17 -05:00
Maciej W. Rozycki a4c4834545
target-mips: Fix CP0.Config3.ISAOnExc write accesses
Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This
bit is mandatory for any processor that implements the microMIPS
instruction set. This bit is r/w for processors that implement both the
standard MIPS and the microMIPS instruction set. This bit is r/o and
hardwired to 1 if only the microMIPS instruction set is implemented.

There is no other bit ever writable in CP0.Config3 so defining a
corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I
think an overkill. Therefore make the ability to write the bit rely on
the presence of ASE_MICROMIPS set in the instruction flags.

The read-only case of the microMIPS instruction set being implemented
only can be added when we add support for such a configuration. We do
not currently have such support, we have no instruction flag that would
control the presence of the standard MIPS instruction set nor any
associated code in instruction decoding.

This change is needed to boot a microMIPS Linux kernel successfully,
otherwise it hangs early on as interrupts are enabled and then the
exception handler invoked loops as its first instruction is interpreted
in the wrong execution mode and triggers another exception right away.
And then over and over again.

We already check the current setting of the CP0.Config3.ISAOnExc in
`set_hflags_for_handler' to set the ISA bit correctly on the exception
handler entry so it is the ability to set it that is missing only.

Backports commit 90f12d735d66ac1196d9a2bced039a432eefc03d from qemu
2018-02-11 16:24:19 -05:00
Maciej W. Rozycki 611933d18d
target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP
Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
using register addition operations.

This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands
to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying
`rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a
sign-extension from bit #31 is made, unless in the uninteresting case of
`rs' being 0, losing the upper 32 bits of the value copied for any
proper 64-bit values.

This also serves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).

Backports commit 7215d7e7aea85699bf516c3e8d84f6a22584da35 from qemu
2018-02-11 16:17:41 -05:00
Maciej W. Rozycki 45c45541d0
target-mips: Correct the writes to Status and Cause registers via gdbstub
Make writes to CP0.Status and CP0.Cause have the same effect as
executing corresponding MTC0 instructions would in Kernel Mode. Also
ignore writes in the user emulation mode.

Currently for requests from the GDB stub we write all the bits across
both registers, ignoring any read-only locations, and do not synchronise
the environment to evaluate side effects. We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.

Backports commit 81a423e6c6d3ccaa79de4e58024369c660c1eeb4 from qemu
2018-02-11 16:16:16 -05:00
Lioncash 8f64168d1f
target-mips: Correct the handling of writes to CP0.Status for MIPSr6
Correct these issues with the handling of CP0.Status for MIPSr6:

* only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that
is for processors that do implement Supervisor Mode, let the bit
pattern be written to CP0.Status.UM:R0 freely (of course the value
written to read-only CP0.Status.R0 will be discarded anyway); this is
in accordance to the relevant architecture specification[1],

* check the newly written pattern rather than the current contents of
CP0.Status for the KSU bits being 0b11,

* use meaningful macro names to refer to CP0.Status bits rather than
magic numbers.

References:

[1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64
Privileged Resource Architecture", MIPS Technologies, Inc., Document
Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status
Register Field Descriptions", pp. 210-211.

Backports commit f88f79ec9df06d26d84e1d2e0c02d2634b4d8583 from qemu
2018-02-11 16:10:54 -05:00
Maciej W. Rozycki 4d9107be8a
target-mips: Correct MIPS16/microMIPS branch size calculation
Correct MIPS16/microMIPS branch size calculation in PC adjustment
needed:

- to set the value of CP0.ErrorEPC at the entry to the reset exception,

- for the purpose of branch reexecution in the context of device I/O.

Follow the approach taken in `exception_resume_pc' for ordinary, Debug
and NMI exceptions.

MIPS16 and microMIPS branches can be 2 or 4 bytes in size and that has
to be reflected in calculation. Original MIPS ISA branches, which is
where this code originates from, are always 4 bytes long, just as all
original MIPS ISA instructions.

Backports commit c3577479815f5bcf9d38993967bca2115af245d8 from qemu
2018-02-11 16:09:33 -05:00
Lioncash 283cbd0317
target-mips: Restore the order of helpers
Restore the order of helpers that used to be: unary operations (generic,
then MIPS-specific), binary operations (generic, then MIPS-specific),
compare operations. At one point FMA operations were inserted at a
random place in the file, disregarding the preexisting order, and later
on even more operations sprinkled across the file. Revert the mess by
moving FMA operations to a new ternary class inserted after the binary
class and move the misplaced unary and binary operations to where they
belong.

Backports commit 8fc605b8aa257feb3e69d44794a765bd492b573b from qemu
2018-02-11 16:07:02 -05:00
Maciej W. Rozycki 802b5d9a3d
target-mips: Remove unused 'FLOAT_OP' macro
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].

Backports commit 51fdea945ae7adae8d7e4a1624e35bb7f714b58f from qemu
2018-02-11 16:03:56 -05:00
Lioncash f62664948e
target-mips: Make 'helper_float_cvtw_s' consistent with the remaining helpers
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.

Backports commit 2b09f94cdbf5c54e2278d7f3aed2eceff3494790 from qemu
2018-02-11 16:02:38 -05:00
Maciej W. Rozycki 0f82a7f89f
target-mips: assorted formatting fixes
Backports commits d75de74967f631a7d0b538d4b88f96f9c426bfe2, 6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85, and d2bfa6e6222baa0218bd0658499d38bac56ac34c from qemu
2018-02-11 16:01:23 -05:00
Maciej W. Rozycki ca496991ea
target-mips: Enable vectored interrupt support for the 74Kf CPU
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.

Backports commit 4386f08767240080334539ac0b07a8bfe30bffe9 from qemu
2018-02-11 15:57:17 -05:00
Maciej W. Rozycki 338e34290d
target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors
Add the M14K and M14Kc processors from MIPS Technologies that are the
original implementation of the microMIPS ISA. They are dual instruction
set processors, implementing both the microMIPS and the standard MIPSr32
ISA.

These processors correspond to the M4K and 4KEc CPUs respectively,
except with support for the microMIPS instruction set added, support for
the MCU ASE added and two extra interrupt lines, making a total of 8
hardware interrupts plus 2 software interrupts. The remaining parts of
the microarchitecture, in particular the pipeline, stayed unchanged.

The presence of the microMIPS ASE is is reflected in the configuration
added. We currently have no support for the MCU ASE, including in
particular the ACLR, ASET and IRET instructions in either encoding, and
we have no support for the extra interrupt lines, including bits in
CP0.Status and CP0.Cause registers, so these features are not marked,
making our support diverge from real hardware.

Backports commit 11f5ea105c06bec72e9bc9a700fa65d60afb5ec3 from qemu
2018-02-11 15:56:28 -05:00
Lioncash 833b0ff964
target-mips: Make CP0.Config4 and CP0.Config5 registers signed
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.

Backports commit 8280b12c0e4b515d707509dde4ddde05d9bda4ef from qemu
2018-02-11 15:48:10 -05:00
Maciej W. Rozycki 5eea73c534
target-mips: Add 5KEc and 5KEf MIPS64r2 processors
Add the 5KEc and 5KEf processors from MIPS Technologies that are the
original implementation of the MIPS64r2 ISA.

Silicon for these processors has never been taped out and no soft cores
were released even. They do exist though, a CP0.PRId value has been
assigned and experimental RTLs produced at the time the MIPS64r2 ISA has
been finalized. The settings introduced here faithfully reproduce that
hardware.

As far the implementation goes these processors are the same as the 5Kc
and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather
than the original MIPS64 instruction set. There must have been some
updates to the CP0 architecture as mandated by the ISA, such as the
addition of the EBase register, although I am not sure about the exact
details, no documentation has ever been produced for these processors.
The remaining parts of the microarchitecture, in particular the
pipeline, stayed unchanged. Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.

Backports commit 36b86e0dc2be93fc538fe7e11e0fda1a198f0135 from qemu
2018-02-11 15:47:13 -05:00
Richard Henderson dd1ec408e5
target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets.

Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu
2018-02-11 12:46:30 -05:00
Richard Henderson a64d0ff657
target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.

Backports commit 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 from qemu
2018-02-11 12:41:20 -05:00
Lioncash b3f9ff667b
tcg: Rename debug_insn_start to insn_start
With an eye toward making it mandatory.

Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
2018-02-11 12:34:01 -05:00
Lioncash f8388a6c03
header_gen: Fix mips platform 2018-02-10 23:21:41 -05:00
Richard Henderson a3aaf5a864
tcg: Remove tcg_gen_trunc_i64_i32
Replacing it with tcg_gen_extrl_i64_i32.

Backports commit ecc7b3aa71f5fdcf9ee87e74ca811d988282641d from qemu
2018-02-10 23:11:02 -05:00
Richard Henderson dafc44c0a5
target-mips: Use CPU_LOG_INT for logging related to interrupts
There are now no unconditional uses of qemu_log in the subdirectory.

Backports commit c85570163bdf1ba29cb52a63f22ff1c48f1b9398 from qemu
2018-02-10 21:12:41 -05:00
Richard Henderson 6f66fb4bd5
target-mips: Copy restrictions from ext/ins to dext/dins
The checks in dins is required to avoid triggering an assertion
in tcg_gen_deposit_tl. The check in dext is just for completeness.
Fold the other D cases in via fallthru.

Backports commit b7f26e523914b982a1c1bfa8295f77ff9787c33c from qemu
2018-02-10 21:09:26 -05:00
Richard Henderson 232632e76c
tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu
2018-02-09 14:17:56 -05:00
Lioncash 0273e6ae18
tcg: Put opcodes in a linked list
The previous setup required ops and args to be completely sequential,
and was error prone when it came to both iteration and optimization.
2018-02-09 12:54:05 -05:00
Richard Henderson a41b9acc0c
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
The method by which we count the number of ops emitted
is going to change. Abstract that away into some inlines.

Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.
2018-02-09 09:31:17 -05:00
Richard Henderson 78378289e3
tcg: Move emit of INDEX_op_end into gen_tb_end
Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu
2018-02-09 08:51:01 -05:00
Richard Henderson 6b4b493dae
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.

Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu
2018-02-08 12:33:33 -05:00
Ryan Hileman 1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Nguyen Anh Quynh e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
Nguyen Anh Quynh cb44f77ac3 mips: fix uc_reg_read() for MIPS64 2017-04-12 22:06:26 +08:00
Nguyen Anh Quynh 094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm ccdb0ff523 armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Matt Thomas 2749b8412e fix register widths for MIPS64 reg_read/write (#775)
* fix register widths for MIPS64 reg_read/write

* fix preprocessor typedef error for qemu/target-mips
2017-03-08 08:40:30 +08:00
xorstream 69ae8f7987 Fix for MIPS issue. (#733) 2017-01-23 12:39:34 +08:00
xorstream 72a497bc14 Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream 92392e0f57 Merge with current master. 2017-01-20 18:22:28 +11:00
Nguyen Anh Quynh b678512fc1 remove kvm stuffs 2017-01-20 01:03:59 +08:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh 0640b35943 mips: remove qemu/hw/mips/mips_int.c 2017-01-19 13:07:28 +08:00
Chris Eagle fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695)
* revert to use of g_free to make future qemu integrations easier

* bracing
2016-12-21 22:28:36 +08:00
Chris Eagle e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh c59e06d798 mips: fix some compilation warnings 2016-10-22 13:36:37 +08:00
Nguyen Anh Quynh b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Ryan Hileman cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00
Andrew Dutcher 0ef2b5fd71 New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00
Andrew Dutcher 97b10da133 Undo the disaster that was the patch to unicorn github issue #266 and fix it correctly. makes normal self-modifying code work. 2016-08-09 19:35:20 -07:00
danghvu 27e0699ef5 mips: Fix memleak 2016-07-09 20:16:00 -05:00
Ryan Hileman acd88856e1 add batched reg access 2016-04-04 20:51:38 -07:00
Hiroyuki UEKAWA c5888e5670 move macros in qemu/target-*/unicorn*.c to uc_priv.h 2016-03-02 12:43:02 +09:00
Hiroyuki UEKAWA 1cd3c3093b fix WRITE_BYTE_H 2016-03-02 10:51:50 +09:00
Nguyen Anh Quynh 5a04bcb115 allow to change PC during callback. this solves issue #210 2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh 2341f5dd1a code style 2016-01-26 17:37:48 +08:00
Ryan Hileman 0886ae8ede rework code/block tracing 2016-01-22 18:42:27 -08:00
Ryan Hileman 93052f6566 refactor to allow multiple hooks for one type 2016-01-22 18:41:43 -08:00
Nguyen Anh Quynh 4117a111eb mips: handle hook callback for blikely instruction properly. this fixes issue #330, #331 2015-12-23 01:40:03 +08:00
Nguyen Anh Quynh 4f268febb4 mips: check for exit request after every hooked instruction. this fix issue #329 2015-12-20 12:23:36 +08:00
Nguyen Anh Quynh 8d3265d9e1 mips: remove unused variable is_bc_slot 2015-12-16 23:06:17 +08:00
xorstream 395251d3e8 Fix codehook for MIPS instructions in delay slot 2015-12-15 17:02:56 +11:00
Nguyen Anh Quynh bc63102e50 mips: only patch instruction size when there is a callback on the instruction. this fixes issue #282 2015-12-13 13:11:40 +08:00
Nguyen Anh Quynh 2f297bdd3a handle some errors properly so avoid exit() during initialization. this fixes issue #237 2015-11-12 01:43:41 +08:00
Nguyen Anh Quynh 3a36e327ab support memory redirection, so the issue #217 is fixed 2015-10-27 14:37:03 +08:00
Nguyen Anh Quynh 2b0b4169bc mips: advance PC for SYSCALL instruction. this fixes issue #157 2015-09-28 10:58:43 +08:00
Nguyen Anh Quynh 53ce8f217d mips: handle delay slot better for branch instructions. this should fix issue #155 2015-09-27 15:05:40 +08:00
Nguyen Anh Quynh 886946dcf4 do not use syscall to quit emulation. this can fix issues #147 & #148 2015-09-26 16:49:00 +08:00
Nguyen Anh Quynh 14a01b5186 mips: handle delay slot so do not duplicate calling instruction handler. this fixes issue #133 2015-09-22 11:59:53 +08:00
Nguyen Anh Quynh a853eb6363 mips, m68k: early check to see if the address of BB is the until address 2015-09-22 10:24:26 +08:00
Nguyen Anh Quynh 18b6680e96 mips: disable debug output 2015-09-08 23:56:25 +08:00
Nguyen Anh Quynh 84e3b5c897 cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98 2015-09-04 11:17:08 +08:00
Jonathon Reinhart 3bd705a060 Merge remote-tracking branch 'upstream/master' into change-handle-based-api 2015-08-30 00:23:51 -04:00
Nguyen Anh Quynh b335cf016c do not generate basic-block callback when translation is broken in the middle due to full cache (all the remaining archs) 2015-08-27 21:09:00 +08:00
Jonathon Reinhart 15a774ac90 change uch to uc_struct (target-mips) 2015-08-26 09:02:16 -04:00
Nguyen Anh Quynh cc5d28e112 mips: fix issue #39 2015-08-26 09:39:09 +08:00
Jonathon Reinhart 9163bba812 restore mode of .[ch] files
These were marked as executable in 5c3b6819, likely due to a Windows
filesystem being involved. This can be avoided:
http://stackoverflow.com/q/1580596/119527
2015-08-24 21:19:12 -04:00
Chris Eagle 5c3b681945 Add const to uc_reg_write and derivitives 2015-08-24 09:42:50 -07:00
mothran a167f7c456 renames the register constants so unicorn and capstone can compile together 2015-08-23 21:36:33 -07:00
Nguyen Anh Quynh 344d016104 import 2015-08-21 15:04:50 +08:00