Commit graph

4428 commits

Author SHA1 Message Date
Lioncash bf6dfeb175
target/arm/translate: Synchronize with qemu
Backports a few other missing pieces from mainline qemu.
2019-04-18 06:22:36 -04:00
Lioncash 5b062dacf2
target/arm: Simplify and correct thumb instruction tracing
This wasn't subtracting the size of the instruction off the PC like how
the ARM mode tracing was performing the tracing. This simplifies it and
makes the behavior identical.
2019-04-18 06:00:15 -04:00
Lioncash 5d6ddec7fb
target/arm/translate: Subtract PC value properly for thumb tracecode calls 2019-04-18 05:44:48 -04:00
Lioncash b9d1002609
tcg-op: Make sure to free temporaries within gen_uc_tracecode()
After the helper is generated, these are no longer needed and can be
reclaimed.
2019-04-18 05:40:48 -04:00
Lioncash e579832dcb
tcg: Synchronize with qemu 2019-04-18 04:57:19 -04:00
Lioncash 3521e72580
target/arm: Sychronize with qemu
Synchronizes with bits and pieces that were missed due to merging
incorrectly (sorry :<)
2019-04-18 04:49:11 -04:00
Peter Maydell 753b6601c5
Update version for v4.0.0-rc4 release
Backports commit eeba63fc7fface36f438bcbc0d3b02e7dcb59983 from qemu
2019-04-16 22:39:02 -04:00
Lukas Dresel 4b94a8cc44
support for YMM registers ymm8-ymm15 (#1079)
Backports 55d8d073bd80935e807289ae2ff6161145a2afb6 from qemu
2019-04-16 06:35:41 -04:00
Lioncash 5de5b69344
target/i386: Fix compilation of the x86 target
Thanks to @rk700 for reporting it.
2019-04-16 06:29:06 -04:00
Lioncash ddcf400955
arm: Always enable access to coprocessors initially
Allows non-AArch64 environments to always access coprocessors initially.
Removes the need to do avoidable register management when testing
floating-point code.
2019-04-13 19:49:43 -04:00
Peter Maydell 5bcb1e13ab
Update version for v4.0.0-rc3 release
Backports commit 532cc6da74ec25b5ba6893b5757c977d54582949 from qemu
2019-04-10 15:00:31 -04:00
Peter Maydell 3ff38c2402
include/qemu/bswap.h: Use __builtin_memcpy() in accessor functions
In the accessor functions ld*_he_p() and st*_he_p() we use memcpy()
to perform a load or store to a pointer which might not be aligned
for the size of the type. We rely on the compiler to optimize this
memcpy() into an efficient load or store instruction where possible.
This is required for good performance, but at the moment it is also
required for correct operation, because some users of these functions
require that the access is atomic if the pointer is aligned, which
will only be the case if the compiler has optimized out the memcpy().
(The particular example where we discovered this is the virtio
vring_avail_idx() which calls virtio_lduw_phys_cached() which
eventually ends up calling lduw_he_p().)

Unfortunately some compile environments, such as the fortify-source
setup used in Alpine Linux, define memcpy() to a wrapper function
in a way that inhibits this compiler optimization.

The correct long-term fix here is to add a set of functions for
doing atomic accesses into AddressSpaces (and to other relevant
families of accessor functions like the virtio_*_phys_cached()
ones), and make sure that callsites which want atomic behaviour
use the correct functions.

In the meantime, switch to using __builtin_memcpy() in the
bswap.h accessor functions. This will make us robust against things
like this fortify library in the short term. In the longer term
it will mean that we don't end up with these functions being really
badly-performing even if the semantics of the out-of-line memcpy()
are correct.
2019-04-10 14:57:52 -04:00
Peter Maydell 6b413ffa97
target/i386: Generate #UD for LOCK on a register increment
Fix a TCG crash due to attempting an atomic increment
operation without having set up the address first.
This is a similar case to that dealt with in commit
e84fcd7f662a0d8198703, and we fix it in the same way.

Fixes: https://bugs.launchpad.net/qemu/+bug/1807675

Backports commit 8cb2ca3d7479748587313f0b34034a3f8aa08c92 from qemu
2019-04-09 09:28:46 -04:00
Peter Maydell 1a50ee5826
Update version for v4.0.0-rc2 release
Backports commit 061b51e9195670e9d190cdec46fabcb3c77763fb from qemu
2019-04-03 10:02:46 -04:00
Paolo Bonzini b4dd8afa14
config-all-devices.mak: rebuild on reconfigure
This ensures that softmmu directories are culled after a
"./configure --target-list=x86_64-linux-user".

Backports commit b7c11e574977a0addfbbdb89377c6f52affe64ec from qemu
2019-03-29 19:31:32 -04:00
Singh, Brijesh 54b9701799
memory: Fix the memory region type assignment order
Currently, a callback registered through the RAMBlock notifier
is not able to get the memory region type (i.e callback is not
able to use memory_region_is_ram_device function). This is
because mr->ram assignment happens _after_ the memory is allocated
whereas the callback is executed during allocation.

Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1667249

Backports commit 2ddb89b00f947f785c9ca6742f28f954e3b75e62 from qemu
2019-03-29 19:28:41 -04:00
Peter Maydell d57c77afcf
Update version for v4.0.0-rc1 release
Backports commit 49fc899f8d673dd9e73f3db0d9e9ea60b77c331b from qemu
2019-03-26 20:44:04 -04:00
Richard Henderson f5cb1a5865
target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max
Fixes: https://bugs.launchpad.net/bugs/1821430

Backports commit c8877d0f2f662bf01346a03bc9fd279954b4132d from qemu
2019-03-26 20:41:01 -04:00
Kito Cheng 5a7ad783e9
target/riscv: Fix wrong expanding for c.fswsp
base register is no rs1 not rs2 for fsw.

Backports commit 620455350a8da7cc62ae82cb69dd5c556f744136 from qemu
2019-03-26 20:39:34 -04:00
Palmer Dabbelt fc662c281a
target/riscv: Zero extend the inputs of divuw and remuw
While running the GCC test suite against 4.0.0-rc0, Kito found a
regression introduced by the decodetree conversion that caused divuw and
remuw to sign-extend their inputs. The ISA manual says they are
supposed to be zero extended:

DIVW and DIVUW instructions are only valid for RV64, and divide the
lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as
signed and unsigned integers respectively, placing the 32-bit
quotient in rd, sign-extended to 64 bits. REMW and REMUW
instructions are only valid for RV64, and provide the corresponding
signed and unsigned remainder operations respectively. Both REMW
and REMUW always sign-extend the 32-bit result to 64 bits, including
on a divide by zero.

Here's Kito's reduced test case from the GCC test suite

unsigned calc_mp(unsigned mod)
{
unsigned a,b,c;
c=-1;
a=c/mod;
b=0-a*mod;
if (b > mod) { a += 1; b-=mod; }
return b;
}

int main(int argc, char *argv[])
{
unsigned x = 1234;
unsigned y = calc_mp(x);

if ((sizeof (y) == 4 && y != 680)
|| (sizeof (y) == 2 && y != 134))
abort ();
exit (0);
}

I haven't done any other testing on this, but it does fix the test case.

Backports commit f17e02cd3731bdfe2942d1d0b2a92f26da02408c from qemu
2019-03-26 20:38:17 -04:00
Andrew Jones 8719b3edb3
target/arm: make pmccntr_op_start/finish static
These functions are not used outside helper.c

Backports commit f2b2f53f6429b5abd7cd86bd65747f5f13e195eb from qemu
2019-03-26 20:35:34 -04:00
Andrew Jones 6482182ba5
target/arm: cortex-a7 and cortex-a15 have pmus
cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
them in ID_DFR0. Let's allow them to function. This also enables
the pmu cpu property to work with these cpu types, i.e. we can
now do '-cpu cortex-a15,pmu=off' to remove the pmu.

Backports commit a46118fc16537a593119e5b316052a98514046bb from qemu
2019-03-26 20:34:11 -04:00
Andrew Jones 3c50e72c40
target/arm: fix crash on pmu register access
Fix a QEMU NULL derefence that occurs when the guest attempts to
enable PMU counters with a non-v8 cpu model or a v8 cpu model
which has not configured a PMU.

Backports commit cbbb3041fe2f57a475cef5d6b0ef836118aad106 from qemu
2019-03-26 20:32:49 -04:00
Richard Henderson 2427ace0c0
target/arm: Fix non-parallel expansion of CASP
The second word has been loaded from the unincremented
address since the first commit.

Backports commit a036f5302c13634f3d375615b2949fd1fa1657b6 from qemu
2019-03-26 20:31:01 -04:00
Eduardo Habkost df51e8bbb3
i386: Disable OSPKE on CPU model definitions
Currently, the Cascadelake-Server, Icelake-Client, and
Icelake-Server are always generating the following warning:

qemu-system-x86_64: warning: \
host doesn't support requested feature: CPUID.07H:ECX [bit 4]

This happens because OSPKE was never returned by
GET_SUPPORTED_CPUID or x86_cpu_get_supported_feature_word().
OSPKE is a runtime flag automatically set by the KVM module or by
TCG code, was always cleared by x86_cpu_filter_features(), and
was not supposed to appear on the CPU model table.

Remove the OSPKE flag from the CPU model table entries, to avoid
the bogus warning and avoid returning invalid feature data on
query-cpu-* QMP commands. As OSPKE was always cleared by
x86_cpu_filter_features(), this won't have any guest-visible
impact.

Include a test case that should detect the problem if we introduce
a similar bug again.

Fixes: c7a88b52f62b ("i386: Add new model of Cascadelake-Server")
Fixes: 8a11c62da914 ("i386: Add new CPU model Icelake-{Server,Client}")

Backports commit bb4928c7cafe50ab2137a0034e350ef1bfa044d9 from qemu
2019-03-22 09:46:44 -04:00
Eduardo Habkost a71df717c9
i386: Make arch_capabilities migratable
Now that kvm_arch_get_supported_cpuid() will only return
arch_capabilities if QEMU is able to initialize the MSR properly,
we know that the feature is safely migratable.

Backports commit 014018e19b3c54dd1bf5072bc912ceffea40abe8 from qemu
2019-03-22 09:45:43 -04:00
Peter Maydell db02d0b733
Update version for v4.0.0-rc0 release
Backports commit 62a172e6a77d9072bb1a18f295ce0fcf4b90a4f2 from qemu
2019-03-19 23:58:31 -04:00
Alistair Francis a9cc62cb23
target/riscv: Remove unused struct
Backports commit 6b745d4fada5c73db44f596a62e29a5dbe3fc53f from qemu
2019-03-19 23:58:31 -04:00
Michael Clark b247ee234d
RISC-V: Update load reservation comment in do_interrupt
Backports commit d9360e96885dbd69ce4aa925d1701c7a10cf54ae from qemu
2019-03-19 23:58:31 -04:00
Michael Clark d3dbcb6dfc
RISC-V: Add support for vectored interrupts
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-19 23:58:31 -04:00
Michael Clark 8ffa68e757
RISC-V: Change local interrupts from edge to level
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- https://github.com/riscv/riscv-qemu/issues/132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

echo 1 > /sys/devices/system/cpu/cpu2/online
echo 0 > /sys/devices/system/cpu/cpu2/online
echo 1 > /sys/devices/system/cpu/cpu2/online

Backports commit d26f5a423438e579d3ff0ca35e44edb966a36233 from qemu
2019-03-19 23:58:31 -04:00
Kito Cheng bd3e9ebaea
RISC-V: linux-user support for RVE ABI
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Backports relevant parts of 5836c3eccedb6dfab16b8f606f2de24b8938b69c
from qemu
2019-03-19 23:58:31 -04:00
Michael Clark 2e0c040062
RISC-V: Allow interrupt controllers to claim interrupts
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
2019-03-19 23:48:12 -04:00
Alistair Francis a4f2dcde28
riscv: pmp: Log pmp access errors as guest errors
Backports commit aad5ac2311f3ad2c0be12d0eaaf4ef4398438fc2 from qemu
2019-03-19 23:45:03 -04:00
Jim Wilson 65903cf9a4
RISC-V: Add debug support for accessing CSRs.
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.

Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-19 23:42:48 -04:00
Jim Wilson 30ab335bb3
RISC-V: Fixes to CSR_* register macros.
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu
2019-03-19 23:39:49 -04:00
Bastian Koppelmann c0f036578c
target/riscv: Fix manually parsed 16 bit insn
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Backports commit f330433b3633647b047cfa418c2ca4d18fda69c7 from qemu
2019-03-19 05:44:58 -04:00
Amir Charif 2392d8b8ab
target/arm: Check access permission to ADDVL/ADDPL/RDVL
These instructions do not trap when SVE is disabled in EL0,
causing them to be executed with wrong size information.

Backports commit 5de56742a3c91de3d646326bec43a989bba83ca4 from qemu
2019-03-19 05:42:59 -04:00
Dongjiu Geng 4dc3d59fd3
target/arm: change arch timer registers access permission
Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.

When VM access registers, QEMU firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to read only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.

Backports commit daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a from qemu
2019-03-19 05:40:44 -04:00
Bastian Koppelmann e96282eb28
target/riscv: Remove decode_RV32_64G()
decodetree handles all instructions now so the fallback is not necessary
anymore.

Backports commit 25e6ca30c668783cd72ff97080ff44e141b99f9b from qemu
2019-03-19 05:37:42 -04:00
Bastian Koppelmann a371684da9
target/riscv: Remove gen_system()
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Backports commit 8f7bc273868939f0821e07fb23792db63d45bffb from qemu
2019-03-19 05:36:48 -04:00
Bastian Koppelmann 1765e6a090
target/riscv: Rename trans_arith to gen_arith
Backports commit 8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3 from qemu
2019-03-19 05:35:44 -04:00
Bastian Koppelmann 28daad082b
target/riscv: Remove manual decoding of RV32/64M insn
Backports commit 1288701682d81b93f62e01cd87001dc90b30b881 from qemu
2019-03-19 05:34:32 -04:00
Bastian Koppelmann b9eda7c464
target/riscv: Remove shift and slt insn manual decoding
Backports commit 34446e845829f55eaa9a07a915950af0b2710b47 from qemu
2019-03-19 05:23:47 -04:00
Bastian Koppelmann 177726afb8
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu
2019-03-19 05:17:54 -04:00
Bastian Koppelmann cb7c94fbc4
target/riscv: Move gen_arith_imm() decoding into trans_* functions
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.

Backports commit 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 from qemu
2019-03-19 05:14:21 -04:00
Bastian Koppelmann 6190837e2f
target/riscv: Remove manual decoding from gen_store()
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Backports commit bce8a342a1f0919479d18ec812b100136daa746b from qemu
2019-03-19 05:05:14 -04:00
Bastian Koppelmann f91f286ed2
target/riscv: Remove manual decoding from gen_load()
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.

Backports commit 98898b20e9cca462843c22ad952c216ffd57d654 from qemu
2019-03-19 05:02:25 -04:00
Bastian Koppelmann 6f89816f5d
target/riscv: Remove manual decoding from gen_branch()
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Backports commit 090cc2c898a04e42350eabf1bcf7d245471603f9 from qemu
2019-03-19 04:59:08 -04:00
Bastian Koppelmann 3fe4cf353c
target/riscv: Remove gen_jalr()
trans_jalr() is the only caller, so move the code into trans_jalr().

Backports commit 9e92c57d834cd50ab088d75510c3c720878eef13 from qemu
2019-03-19 04:55:52 -04:00
Bastian Koppelmann 580457a1d2
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 04:53:07 -04:00
Bastian Koppelmann b4854e3340
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 04:50:08 -04:00
Lioncash 8d294a7897
target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-19 04:45:53 -04:00
Bastian Koppelmann 67164f2b29
target/riscv: Convert RV priv insns to decodetree
Backports commit 4ba79c47a205b3af4b62b9b1b6090dee678a1069 from qemu
2019-03-19 04:40:24 -04:00
Bastian Koppelmann 7475207aba
target/riscv: Convert RV64D insns to decodetree
Backports commit 31fe4d35f2608daecb2319c81e0bb4af81b398ae from qemu
2019-03-18 16:57:16 -04:00
Bastian Koppelmann 71f2ed2959
target/riscv: Convert RV32D insns to decodetree
Backports commit 97f8b49372d73aab4d172df4ea297d7f3ce4e02e from qemu
2019-03-18 16:51:20 -04:00
Bastian Koppelmann d8d107ec85
target/riscv: Convert RV64F insns to decodetree
Backports commit 95561ee3b41a536cc373e59da10605e2a8676ee2 from qemu
2019-03-18 16:43:17 -04:00
Bastian Koppelmann 9edaf2069e
target/riscv: Convert RV32F insns to decodetree
Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 16:40:04 -04:00
Bastian Koppelmann 3f9177f6e7
target/riscv: Convert RV64A insns to decodetree
Backports commit 40b9faecfe8000520958f50a77ea16f4b3dd6405 from qemu
2019-03-18 16:27:53 -04:00
Bastian Koppelmann 81013f9e2b
target/riscv: Convert RV32A insns to decodetree
Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 16:25:50 -04:00
Bastian Koppelmann 3a5da0b939
target/riscv: Convert RVXM insns to decodetree
Backports commit d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 from qemu
2019-03-18 16:20:29 -04:00
Bastian Koppelmann 4ea449a809
target/riscv: Convert RVXI csr insns to decodetree
Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu
2019-03-18 16:17:59 -04:00
Bastian Koppelmann de580ee378
target/riscv: Convert RVXI fence insns to decodetree
Backports commit 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed from qemu
2019-03-18 16:09:21 -04:00
Bastian Koppelmann 11e2b9c410
target/riscv: Convert RVXI arithmetic insns to decodetree
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.

Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 16:04:49 -04:00
Bastian Koppelmann 1024ceb4df
target/riscv: Convert RV64I load/store insns to decodetree
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu
2019-03-18 16:02:16 -04:00
Bastian Koppelmann 65a415372b
target/riscv: Convert RV32I load/store insns to decodetree
Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 15:59:43 -04:00
Bastian Koppelmann 55dc0038e8
target/riscv: Convert RVXI branch insns to decodetree
Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 15:58:16 -04:00
Bastian Koppelmann 5e5b3e9ea9
target/riscv: Activate decodetree and implemnt LUI & AUIPC
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.

Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 15:54:17 -04:00
Richard Henderson 4111a3a892
decodetree: Properly diagnose fields overflowing an insn
Previously this would result in an exception for shifting
the field mask by a negative number.

Backports commit 2decfc95583dc28add69810eaca6ada7b4b44d3a from qemu
2019-03-13 11:21:04 -04:00
Richard Henderson fcb49bb6f6
decodetree: Prefix extract function names with decode_function
This makes it easier to name Formats within multiple decode files.

Backports commit 71ecf79bf40db20237a3cfc01cc407cc4cad8817 from qemu
2019-03-13 11:20:26 -04:00
Richard Henderson 1f57e9bedc
decodetree: Allow +- to begin a number initializing a field
Backports commit 263ac638a76a72841e3f513b14c515680703e084 from qemu
2019-03-13 11:19:56 -04:00
Richard Henderson e18e116ce5
decodetree: Produce clean output for an empty input file
This is interesting for bisection, where an output file is plumbed,
but does not yet have patterns.

Backports commit 82bfac1c06cadeb5c7252734dc695d951185916c from qemu
2019-03-13 11:19:22 -04:00
Richard Henderson 190ee1657b
decodetree: Add --static-decode option
Like --decode, but do not drop 'static' qualifier.

Backports commit cd3e7fc18db43b296f413814cd4b72bcd6878bc4 from qemu
2019-03-13 11:18:43 -04:00
Richard Henderson c8514cc538
decodetree: Allow grouping of overlapping patterns
Backports commit 0eff2df4a2ce677230119440f7eb057acffad5eb from qemu
2019-03-13 11:17:48 -04:00
Richard Henderson 0c1b2a5d5a
decodetree: Do not unconditionaly return from Pattern.output_code
As a consequence, the 'return false' gets pushed up one level.

This will allow us to perform some other action when the
translator returns failure.

Backports commit eb6b87fac70dd62e3f1286703db20c012e7a9611 from qemu
2019-03-13 11:13:48 -04:00
Philippe Mathieu-Daudé edb21478b7
decodetree: Ensure build_tree does not include values outside insnmask
Reproduced with "scripts/decodetree.py /dev/null".

Backports commit 9b3186e38f00ae0cba36c096e3654f916699f336 from qemu
2019-03-13 11:12:24 -04:00
Wei Yang 20994eca53
exec.c: refactor function flatview_add_to_dispatch()
flatview_add_to_dispatch() registers page based on the condition of
*section*, which may looks like this:

|s|PPPPPPP|s|

where s stands for subpage and P for page.

The procedure of this function could be described as:

- register first subpage
- register page
- register last subpage

This means the procedure could be simplified into these three steps
instead of a loop iteration.

This patch refactors the function into three corresponding steps and
adds some comment to clarify it.

Backports commit 494d199727ba248c96326b4e1c97f86eb11a5ec7 from qemu
2019-03-11 17:00:46 -04:00
Philippe Mathieu-Daudé 963beb216d
configure: Disable W^X on OpenBSD
Since OpenBSD 6.0 [1], W^X is enforced by default [2].
TCG requires WX access. Disable W^X if it is available.
This fixes:

\# lm32-softmmu/qemu-system-lm32
Could not allocate dynamic translator buffer

\# sysctl kern.wxabort=1
kern.wxabort: 0 -> 1
\# lm32-softmmu/qemu-system-lm32
mmap: Not supported
Abort trap (core dumped)
\# gdb -q lm32-softmmu/qemu-system-lm32 qemu-system-lm32.core
(gdb) bt
\#0 0x000017e3c156c50a in _thread_sys___syscall () at {standard input}:5
\#1 0x000017e3c15e5d7a in *_libc_mmap (addr=Variable "addr" is not available.) at /usr/src/lib/libc/sys/mmap.c:47
\#2 0x000017e17d9abc8b in alloc_code_gen_buffer () at /usr/src/qemu/accel/tcg/translate-all.c:1064
\#3 0x000017e17d9abd04 in code_gen_alloc (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1112
\#4 0x000017e17d9abe81 in tcg_exec_init (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1149
\#5 0x000017e17d9897e9 in tcg_init (ms=0x17e45e456800) at /usr/src/qemu/accel/tcg/tcg-all.c:66
\#6 0x000017e17d9891b8 in accel_init_machine (acc=0x17e3c3f50800, ms=0x17e45e456800) at /usr/src/qemu/accel/accel.c:63
\#7 0x000017e17d989312 in configure_accelerator (ms=0x17e45e456800, progname=0x7f7fffff07b0 "lm32-softmmu/qemu-system-lm32") at /usr/src/qemu/accel/accel.c:111
\#8 0x000017e17d9d8616 in main (argc=1, argv=0x7f7fffff06b8, envp=0x7f7fffff06c8) at vl.c:4325

[1] https://www.openbsd.org/faq/upgrade60.html
[2] https://undeadly.org/cgi?action=article&sid=20160527203200

Backports commit 7776ea6b49873ed18a2111e25ed8a6d94bd73db8 from qemu
2019-03-11 16:46:52 -04:00
Luwei Kang 9f2ce63414
i386: extended the cpuid_level when Intel PT is enabled
Intel Processor Trace required CPUID[0x14] but the cpuid_level
have no change when create a kvm guest with
e.g. "-cpu qemu64,+intel-pt

Backports relevant bits of commit
f24c3a79a415042f6dc195f029a2ba7247d14cac from qemu
2019-03-11 16:40:23 -04:00
Lioncash d6b706a296
qemu/fpu: Synchronize with Qemu
Resolves a few formatting discrepancies
2019-03-09 18:27:31 -05:00
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
2019-03-08 21:46:10 -05:00
yhql 1723cb1015
Add ARM MSP, PSP and CONTROL register access (#1071)
Necessary for NVIC exception emulation from user.

Backports commit 31851280316d37305f412fff42f45bb375999074 from unicorn
2019-03-08 02:24:49 -05:00
Lioncash 8f688748c4
translate/i386: Restore Qemu's ordering of CPU and cache definitions
Like the previous two changes, this restores the layout of Qemu's
designated initializers.
2019-03-08 01:51:27 -05:00
Lioncash 1ddbb253e2
target/mips: Restore Qemu's organization of CPU definitions
Like 5075a0158a, this restores Qemu's
formatting of the processor tables to make it significantly less
annoying to maintain.
2019-03-08 01:40:50 -05:00
Lioncash 5075a0158a
target/arm: Restore Qemu's organization of coprocessor registers
These changes were mostly made in upstream unicorn for what I can guess,
was to support old versions of MSVC's compiler.

This is also a pain to maintain, since everything needs to be done
manually and can be a source of errors. It also makes it take more work
than it needs to, to backport changes from qemu.

Because of that, this change restores Qemu's organization of the
coprocessor registers.
2019-03-08 01:32:47 -05:00
Richard Henderson f116560d2c
target/arm: Implement ARMv8.5-FRINT
Backports 6bea25631af92531027d3bf3ef972a4d51d62e7c from qemu.
2019-03-05 23:17:33 -05:00
Richard Henderson f855ac073d
target/arm: Restructure handle_fp_1src_{single, double}
This will allow sharing code that adjusts rmode beyond
the existing users.

Backports commit 0e4db23d1fdbfed4fc1ec19b6e59820209600358 from qemu
2019-03-05 23:09:48 -05:00
Richard Henderson 94b5aab8f8
target/arm: Implement ARMv8.5-CondM
Backports commit 5ef84f111483e3f7b57efc690e22081ca8f99544 from qemu
2019-03-05 23:04:06 -05:00
Richard Henderson 1dfa15a683
target/arm: Implement ARMv8.4-CondM
Backports commit b89d9c988a988d5547c73e2bc43f59b0c07420a5 from qemu
2019-03-05 22:59:51 -05:00
Richard Henderson 65a3f3be5b
target/arm: Rearrange disas_data_proc_reg
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.

In particular, op2 == 0 is now more than just Add/sub (with carry).

Backports commit 2fba34f70d9a81bab56e61bb99a4d6632bdfe531 from qemu
2019-03-05 22:55:27 -05:00
Richard Henderson 45c297c99b
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Backports commit 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 from qemu
2019-03-05 22:55:22 -05:00
Richard Henderson 60742608f5
target/arm: Split helper_msr_i_pstate into 3
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.

Backports commit ff730e9666a716b669ac4a8ca7c521177d1d2b15 from qemu
2019-03-05 22:45:11 -05:00
Richard Henderson 5d42ca6a65
target/arm: Implement ARMv8.0-PredInv
Backports commit cb570bd318beb2ecce83cabf8016dacceb824dce from qemu
2019-03-05 22:37:57 -05:00
Richard Henderson 1721e429c2
target/arm: Implement ARMv8.0-SB
Backports commit 9888bd1e20425dfe4dcca5dcd1ca2fac8e90ad19 from qemu
2019-03-05 22:35:16 -05:00
Richard Henderson a552a7b2e0
target/arm: Split out arm_sctlr
Minimize the number of places that will need updating when
the virtual host extensions are added.

Backports commit 64e40755cd41fbe8cd266cf387e42ddc57a449ef from qemu
2019-03-05 22:29:25 -05:00
Richard Henderson fa70a2bc69
target/arm: Fix PC test for LDM (exception return)
Found by inspection: Rn is the base register against which the
load began; I is the register within the mask being processed.
The exception return should of course be processed from the loaded PC.

Backports commit 9d090d17234058f55c3c439d285db78c94d7d4de from qemu
2019-03-05 22:27:38 -05:00
Lioncash 7a6f61057b
target/m68k: Correct instruction emulation
Previously we weren't even initializing the instruction table, so any
attempt at emulation would cause a segmentation fault.

This also moves the end address check after the decoding to correctly
perform exiting behavior with the new translator model.
2019-02-28 19:21:49 -05:00
Lioncash 0868015992
target/arm: Move TCGContext variable within arm_post_translate_insn into a narrower scope
This is only used within the scope of the if statement, so we can just
move it there.
2019-02-28 18:53:33 -05:00
Lioncash 15440a83c5
target/arm: Fix execution of ARM instructions
Previously we'd be checking prior to the actual decoding if we were at
the ending address. This worked fine using the old model of the
translation process in qemu. However, this causes the wrong behavior to
occur in both ARM and Thumb/Thumb-2 modes using the newer translator
model.

Given the translator itself checks for the end address already, this
needs to be placed within arm_post_translate_insn().

This prevents the emulation process being off-by-one as well when it
comes to actually executing the instructions.
2019-02-28 18:49:22 -05:00
dmarxn 7164ab5ff4
changed cpu_compue_eflags to use the updated eflags variable. Otherwise, cli/sti and popfl may break, as we get the non-updated eflags (#1057)
Backports commit 360e9c60e1feb4a93e7e43f30858e38eac2d35f2 from unicorn
2019-02-28 17:05:13 -05:00
nanoric 245d2070fe
[Fix] Add feature support for CMPXCHG16B instruction. (#983)
Backports commit 2a240079d8fa4f1c77208379338c676ac6bf18ce from unicorn
2019-02-28 17:03:08 -05:00
nanoric 9e8e5645fc
[Fix] Fix a problem that use uc_reg_write to write fs, gs has no effets in x86 64-bit mode. (#984)
Backports commit a2493a0d4121b671fe9d16e41a9bdd3307b7b1ef from unicorn.
2019-02-28 16:52:54 -05:00
BrunoPujos 1d4bfd9aca
i386: set MSR IA32_EFER to correct value at init for IA32e Mode (#1047)
Backports commit 536c4e77c4350fac3e5c2b9b57d8c16f69b934d3 from unicorn.
2019-02-28 16:49:31 -05:00
cfrantz 5ad3a0ea82
Add support for the ARM IPSR register. (#1067)
1. Create an enum name for the IPSR register.
2. Implement read and write of the IPSR via the xpsr helper functions.

Fixes #1065

Backports commit 6c319941a5462ee3a4af4593c371f5674394d6ce from unicorn.
2019-02-28 16:40:54 -05:00
dmarxn cdcd026413
target/i386: Added MXCSR register, fixed writing to FPUCW. (#1059)
* Added MXCSR register for reading and writing
* Changed writing for fpucw register, now the qemu rounding status is updated as well

Backports commit 256e7782ceafb1f8915da167040d5368c38f9585 from unicorn
2019-02-28 16:31:22 -05:00
Lioncash 2b5d424ded
target/mips: Amend botched rename 2019-02-28 16:21:09 -05:00
Mateja Marjanovic d50a1fef6b
target/mips: Preparing for adding MMI instructions
Set up MMI code to be compiled only for TARGET_MIPS64. This is
needed so that GPRs are 64 bit, and combined with MMI registers,
they will form full 128 bit registers.

Backports commit 37b9aae2e6e005e6df206a0b4804972460806166 from qemu
2019-02-28 16:15:47 -05:00
Richard Henderson fbe1ee25ff
target/arm: Enable ARMv8.2-FHM for -cpu max
Backports commit 991c05995a7bbafbebc1e4d405e947f2edcee063 from qemu
2019-02-28 15:47:03 -05:00
Richard Henderson 4ae3ff8e61
target/arm: Implement VFMAL and VFMSL for aarch32
Backports commit 87732318c5d68a366fc2d6fc394d9c20412099fa from qemu
2019-02-28 15:44:59 -05:00
Richard Henderson 625d3f3cfb
target/arm: Implement FMLAL and FMLSL for aarch64
Backports commit 0caa5af802ff622c854ff4ee2e2b8cdd135b4d73 from qemu
2019-02-28 15:36:41 -05:00
Richard Henderson 5473c3603f
target/arm: Add helpers for FMLAL
Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected. Thus float16_to_float32_by_bits.

Backports commit a4e943a716d5fac923d82df3eabc65d1e3624019 from qemu
2019-02-28 15:31:48 -05:00
Peter Maydell 82b8e97f76
target/arm: Gate "miscellaneous FP" insns by ID register field
There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.

Backports commit c0c760afe800b60b48c80ddf3509fec413594778 from qemu
2019-02-28 15:26:27 -05:00
Peter Maydell 118a2bde5c
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.

This change doesn't alter behaviour for any of our CPUs.

Backports commit 602f6e42cfbfe9278be34e9b91d2ceb695837e02 from qemu
2019-02-28 15:23:51 -05:00
Lioncash 4f210d0731
header_gen: Add float128_to_uint32 to the list
Avoids multiple definition errors.
2019-02-28 15:19:44 -05:00
Richard Henderson 11679ff3cf
softfloat: Support float_round_to_odd more places
Previously this was only supported for roundAndPackFloat64.

New support in round_canonical, round_to_int, float128_round_to_int,
roundAndPackFloat32, roundAndPackInt32, roundAndPackInt64,
roundAndPackUint64. This does not include any of the floatx80 routines,
as we do not have users for that rounding mode there.

Backports commit 5d64abb32ffe558e616545819f3e53dd66335994 from qemu
2019-02-28 15:17:38 -05:00
David Hildenbrand 7373819b1a
softfloat: Implement float128_to_uint32
Handling it just like float128_to_uint32_round_to_zero, that hopefully
is free of bugs :)

Documentation basically copied from float128_to_uint64

Backports commit e45de9922e43c1ce4f4739b62142314a13029d5c from qemu
2019-02-28 15:13:09 -05:00
David Hildenbrand 24a2bd702c
softfloat: add float128_is_{normal,denormal}
Needed on s390x, to test for the data class of a number. So it will
gain soon a user.

A number is considered normal if the exponent is neither 0 nor all 1's.
That can be checked by adding 1 to the exponent, and comparing against
>= 2 after dropping an eventual overflow into the sign bit.

While at it, convert the other floatXX_is_normal functions to use a
similar, less error prone calculation, as suggested by Richard H.

Backports commit 47393181604d507f4fe2a15a65b1eede0f974d6a from qemu
2019-02-28 15:11:50 -05:00
Lioncash b9da32241b
header_gen: Correct multiple definition errors 2019-02-27 17:03:28 -05:00
Lioncash f2ff870171
Fix arm build 2019-02-22 21:00:04 -05:00
David Hildenbrand 8583c8f1f6
include/exec/helper-head.h: support "const void *" in helper calls
Especially when dealing with out-of-line gvec helpers, it is often
helpful to specify some vector pointers as constant. E.g. when
we have two inputs and one output, marking the two inputs as consts
pointers helps to avoid bugs.

Const pointers can be specified via "cptr", however behave in TCG just
like ordinary pointers. We can specify helpers like:

DEF_HELPER_FLAGS_4(gvec_vbperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3,
uint32_t desc)

And make sure that here, only v1 will be written (as long as const is
not casted away, of course).

Backports commit 8c6edfdd90522caa4fc429144d393aba5b99f584 from qemu
2019-02-22 19:12:09 -05:00
Richard Henderson b9156a0f55
tcg: Remove TODO file
The last update to this file was 9 years ago. In the meantime,
4 of the 6 ideas have actually been completed. The lat two do
not actually make sense anymore.

Backports commit 9e564a1dde5abc7ae4cebc115142f685d98938d7 from qemu
2019-02-22 19:10:26 -05:00
Richard Henderson c9ad233678
target/arm: Implement ARMv8.3-JSConv
Backports commit 6c1f6f2733a7692793135ea5ce72b829add99a50 from qemu
2019-02-22 19:08:57 -05:00
Richard Henderson f16dcbe226
target/arm: Rearrange Floating-point data-processing (2 regs)
There are lots of special cases within these insns. Split the
major argument decode/loading/saving into no_output (compares),
rd_is_dp, and rm_is_dp.

We still need to special case argument load for compare (rd as
input, rm as zero) and vcvt fixed (rd as input+output), but lots
of special cases do disappear.

Now that we have a full switch at the beginning, hoist the ISA
checks from the code generation.

Backports commit e80941bd64cc388554770fd72334e9e7d459a1ef from qemu
2019-02-22 18:57:25 -05:00
Richard Henderson dbe623dacc
target/arm: Split out vfp_helper.c
Move all of the fp helpers out of helper.c into a new file.
This is code movement only. Since helper.c has no copyright
header, take the one from cpu.h for the new file.

Backports commit 37356079fcdb34e13abbed8ea0c00ca880c31247 from qemu
2019-02-22 18:48:44 -05:00
Richard Henderson d6fbc0f4f3
target/arm: Restructure disas_fp_int_conv
For opcodes 0-5, move some if conditions into the structure
of a switch statement. For opcodes 6 & 7, decode everything
at once with a second switch.

Backports commit 3c3ff68492c2d00bd8cb39ed2d02bdaf5caf5cb8 from qemu
2019-02-22 18:39:08 -05:00
Aaron Lindsay OS 5c153537f5
target/arm: Stop unintentional sign extension in pmu_init
This was introduced by
commit bf8d09694ccc07487cd73d7562081fdaec3370c8
target/arm: Don't clear supported PMU events when initializing PMCEID1
and identified by Coverity (CID 1398645).

Backports commit 67da43d668320e1bcb0a0195aaf2de4ff2a001a0 from qemu
2019-02-22 18:32:10 -05:00
Peter Maydell 928f226ed6
target/arm: v8M MPU should use background region as default, not always
The "background region" for a v8M MPU is a default which will be used
(if enabled, and if the access is privileged) if the access does
not match any specific MPU region. We were incorrectly using it
always (by putting the condition at the wrong nesting level). This
meant that we would always return the default background permissions
rather than the correct permissions for a specific region, and also
that we would not return the right information in response to a
TT instruction.

Move the check for the background region to the same place in the
logic as the equivalent v8M MPUCheck() pseudocode puts it.
This in turn means we must adjust the condition we use to detect
matches in multiple regions to avoid false-positives.

Backports commit cff21316c666c8053b1f425577e324038d0ca30d from qemu
2019-02-22 18:30:44 -05:00
Markus Armbruster 6279d604d3
qapi: Prepare for system modules other than 'builtin'
The next commit wants to generate qapi-emit-events.{c.h}. To enable
that, extend QAPISchemaModularCVisitor to support additional "system
modules", i.e. modules that don't correspond to a (user-defined) QAPI
schema module.

Backports commit c2e196a9b41235a308fb6d1c516aa91ba0a807c8 from qemu
2019-02-21 09:58:54 -05:00
Markus Armbruster 5d0966ce6b
qapi: Clean up modular built-in code generation a bit
We neglect to call .visit_module() for the special module we use for
built-ins. Harmless, but clean it up anyway. The
tests/qapi-schema/*.out now show the built-in module as 'module None'.

Subclasses of QAPISchemaModularCVisitor need to ._add_module() this
special module to enable code generation for built-ins. When this
hasn't been done, QAPISchemaModularCVisitor.visit_module() does
nothing for the special module. That looks like built-ins could
accidentally be generated into the wrong module when a subclass
neglects to call ._add_module(). Can't happen, because built-ins are
all visited before any other module. But that's non-obvious. Switch
off code generation explicitly.

Rename QAPISchemaModularCVisitor._begin_module() to
._begin_user_module().

New QAPISchemaModularCVisitor._is_builtin_module(), for clarity.

Backports commit dcac64711ea906e844ae60a5927e5580f7252c1e from qemu
2019-02-21 09:56:29 -05:00
Richard Henderson 5c34cab41c
target/arm: Add missing clear_tail calls
Fortunately, the functions affected are so far only called from SVE,
so there is no tail to be cleared. But as we convert more of AdvSIMD
to gvec, this will matter.

Backports commit d8efe78e8039511b95c23d75bb48eca6873fbb0f from qemu
2019-02-15 18:15:20 -05:00
Richard Henderson f3cb92c86c
target/arm: Use vector operations for saturation
For same-sign saturation, we have tcg vector operations. We can
compute the QC bit by comparing the saturated value against the
unsaturated value.

Backports commit 89e68b575e138d0af1435f11a8ffcd8779c237bd from qemu
2019-02-15 18:14:09 -05:00
Richard Henderson 10d468f601
target/arm: Split out FPSCR.QC to a vector field
Change the representation of this field such that it is easy
to set from vector code.

Backports commit a4d5846245c5e029e5aa3945a9bda1de1c3fedbf from qemu
2019-02-15 18:04:13 -05:00
Richard Henderson 356b70e931
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the bits.

Simplify the code in set to also clear the RES0 bits.

Backports commit 18aaa59c622208743565307668a2100ab24f7de9 from qemu
2019-02-15 18:00:57 -05:00
Richard Henderson ca4bb1b4bc
target/arm: Split out flags setting from vfp compares
Minimize the code within a macro by splitting out a helper function.
Use deposit32 instead of manual bit manipulation.

Backports commit 55a889456ef78f3f9b8eae9846c2f1453b1dd77b from qemu
2019-02-15 17:59:34 -05:00
Richard Henderson 4e44043956
target/arm: Fix arm_cpu_dump_state vs FPSCR
Backports commit ec527e4eeccc31e3beadf3b61b66c61bbd873811 from qemu
2019-02-15 17:58:25 -05:00
Richard Henderson ed7c9d0710
target/arm: Remove neon min/max helpers
These are now unused.

Backports commit a5c5dc53c4688efc149b235361d2d49869e77139 from qemu
2019-02-15 17:57:18 -05:00
Richard Henderson 198befc50e
target/arm: Use tcg integer min/max primitives for neon
The 32-bit PMIN/PMAX has been decomposed to scalars,
and so can be trivially expanded inline.

Backports commit 9ecd3c5c1651fa7f9adbedff4806a2da0b50490c from qemu
2019-02-15 17:55:11 -05:00
Richard Henderson eee33bd692
target/arm: Use vector minmax expanders for aarch32
Backports commit 6f2782218230bbb33fa22f9a2f73f8a570046007 from qemu
2019-02-15 17:54:05 -05:00
Richard Henderson 96d1df966b
target/arm: Use vector minmax expanders for aarch64
Backports commit 264d2a481a6c34dfda53be3fbea66116bcef9c5a from qemu
2019-02-15 17:52:36 -05:00
Richard Henderson d147946edc
target/arm: Rely on optimization within tcg_gen_gvec_or
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.

Backports commit 2900847ff4c862887af750935a875059615f509a from qemu
2019-02-15 17:50:28 -05:00
Alex Bennée bf9c8499ca
target/arm: expose remaining CPUID registers as RAZ
There are a whole bunch more registers in the CPUID space which are
currently not used but are exposed as RAZ. To avoid too much
duplication we expand ARMCPRegUserSpaceInfo to understand glob
patterns so we only need one entry to tweak whole ranges of registers.

Backports commit d040242effe47850060d2ef1c461ff637d88a84d from qemu
2019-02-15 17:48:37 -05:00
Alex Bennée 890983f186
target/arm: expose MPIDR_EL1 to userspace
As this is a single register we could expose it with a simple ifdef
but we use the existing modify_arm_cp_regs mechanism for consistency.

Backports commit 522641660c3de64ed8322b8636c58625cd564a3f from qemu
2019-02-15 17:29:23 -05:00
Alex Bennée babf31dfa0
target/arm: expose CPUID registers to userspace
A number of CPUID registers are exposed to userspace by modern Linux
kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's
user-mode emulation we don't need to emulate the kernels trap but just
return the value the trap would have done. To avoid too much #ifdef
hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs)
before defining the registers. The modify routine is driven by a
simple data structure which describes which bits are exported and
which are fixed.

Backports commit 6c5c0fec29bbfe36c64eca1edfd8455be46b77c6 from qemu
2019-02-15 17:27:30 -05:00
Alex Bennée 0a51e5055f
target/arm: relax permission checks for HWCAP_CPUID registers
Although technically not visible to userspace the kernel does make
them visible via a trap and emulate ABI. We provide a new permission
mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
the minimum permission check accordingly.

Backports commit b5bd7440422bb66deaceb812bb9287a6a3cdf10c from qemu
2019-02-15 17:18:06 -05:00
Catherine Ho 841ac2b3bb
target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
The lo,hi order is different from the comments. And in commit
1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128"), it changes
the original code logic. So just restore the old code logic before this
commit:
do_paired_cmpxchg64_be():
cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
newv = int128_make128(new_hi, new_lo);

This fixes a bug that would only be visible for big-endian
AArch64 guest code.

Fixes: 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128")

Backports commit abd5abc58c5d4c9bd23427b0998a44eb87ed47a2 from qemu
2019-02-15 17:16:55 -05:00
Peter Maydell 31813bafe2
target/arm: Implement HACR_EL2
HACR_EL2 is a register with IMPDEF behaviour, which allows
implementation specific trapping to EL2. Implement it as RAZ/WI,
since QEMU's implementation has no extra traps. This also
matches what h/w implementations like Cortex-A53 and A57 do.

Backports commit 831a2fca343ebcd6651eab9102bd7a36b77da65d from qemu
2019-02-15 17:15:41 -05:00
Aaron Lindsay OS af17f7fa59
target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
This bug was introduced in:
commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Backports commit 62c7ec3488fe0dcbabffd543f458914e27736115 from qemu
2019-02-15 17:12:04 -05:00
Leon Alrae 6099733fc5
target/mips: reimplement SC instruction emulation and use cmpxchg
Completely rewrite conditional stores handling. Use cmpxchg.

This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.

Backports commit 33a07fa2db66376e6ee780d4a8b064dc5118cf34 from qemu
2019-02-15 17:10:16 -05:00
Leon Alrae df67716ed5
target/mips: compare virtual addresses in LL/SC sequence
Do only virtual addresses comaprisons in LL/SC sequence emulations.

Until this patch, physical addresses had been compared in SC part of
LL/SC sequence, even though such comparisons could be avoided. Getting
rid of them allows throwing away SC helpers and having common SC
implementations in user and system mode, avoiding the need for two
separate implementations selected by #ifdef CONFIG_USER_ONLY.

Correct guest software should not rely on LL/SC if they accesses the
same physical address via different virtual addresses or if page
mapping gets changed between LL/SC due to manipulating TLB entries.
MIPS Instruction Set Manual clearly says that an RMW sequence must
use the same address in the LL and SC (virtual address, physical
address, cacheability and coherency attributes must be identical).
Otherwise, the result of the SC is not predictable. This patch takes
advantage of this fact and removes the virtual->physical address
translation from SC helper.

lladdr served as Coprocessor 0 LLAddr register which captures physical
address of the most recent LL instruction, and also lladdr was used
for comparison with following SC physical address. This patch changes
the meaning of lladdr - now it will only keep the virtual address of
the most recent LL. Additionally, CP0_LLAddr field is introduced which
is the actual Coperocessor 0 LLAddr register that guest can access.

Backports commit c7c7e1e9a5e3f0a8a1dbff6e4ccfd21c2dc9f845 from qemu
2019-02-15 16:59:40 -05:00
Emilio G. Cota f31764dd5b
cputlb: update TLB entry/index after tlb_fill
We are failing to take into account that tlb_fill() can cause a
TLB resize, which renders prior TLB entry pointers/indices stale.
Fix it by re-doing the TLB entry lookups immediately after tlb_fill.

Fixes: 86e1eff8bc ("tcg: introduce dynamic TLB sizing", 2019-01-28)

Backports commit 6d967cb86d5b4a60ba15b497126b621ce9ca6609 from qemu
2019-02-12 11:48:48 -05:00