Commit graph

260 commits

Author SHA1 Message Date
Aleksandar Markovic 3a276522ac
target/mips: Amend preprocessor constants for CP0 registers
Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).

Backports commit 04992c8cd1c43ecdba39dd8c916db092db6ebae0 from qemu
2019-01-22 19:55:04 -05:00
Yongbok Kim 33e9ea3f10
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
Provide R/W access to SAARI and SAAR CP0 registers.

Backports commit 5fb2dcd17921be71b55fb62d59a12992707d2d3e from qemu
2019-01-22 19:51:38 -05:00
Yongbok Kim 6f850b88e4
target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers.

Backports commit 167db30e981cd72bef15182178037e51afc8e40d from qemu
2019-01-22 19:40:31 -05:00
Aleksandar Markovic c0125e41a1
target/mips: Use preprocessor constants for 32 major CP0 registers
Use preprocessor constants for 32 major CP0 registers.

Backports commit 46d7642fcc97ac108c8080fbe41bc5d00bb537f2 from qemu
2019-01-22 19:38:43 -05:00
Aleksandar Markovic 0feca79dd5
target/mips: Add preprocessor constants for 32 major CP0 registers
Add preprocessor constants for 32 major CP0 registers.

Backports commit efd27d3f08655fc2bcf79a529566aee2cb2e81f8 from qemu
2019-01-22 19:22:39 -05:00
Aleksandar Markovic 9834762d2c
target/mips: Move comment containing summary of CP0 registers
Move comment containing summary of CP0 registers. Checkpatch
script reported some tabs in the resutling diff, so convert
these tabs to spaces too.

Backports commit ea9c5e836e205a87038c8153282d0b6d9234cda2 from qemu
2019-01-22 19:19:54 -05:00
Fredrik Noring ee4b59e981
target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
The three-operand MADD and MADDU are specific to R5900 cores.

Backports commit a95c4c26f1dc233987350e7cb1cf62d46ade5ce5 from qemu
2019-01-05 08:07:56 -05:00
Philippe Mathieu-Daudé 76bc93690f
target/mips: Support R5900 three-operand MADD and MADDU instructions
The three-operand MADD and MADDU are specific to Sony R5900 core,
and Toshiba TX19/TX39/TX79 cores as well.

The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf

Backports commit 3b948f053fc588154d95228da8a6561c61c66104 from qemu
2019-01-05 08:03:43 -05:00
Aleksandar Markovic 5729c803a7
target/mips: MXU: Add handler for an align instruction
Add translation handler for S32ALNI MXU instruction.

Backports commit 79f5fee7a3c53494c7ca4bc18c72944f5e2d5c2f from qemu
2019-01-05 08:00:09 -05:00
Aleksandar Markovic 94956d81f6
target/mips: MXU: Add handlers for max/min instructions
Add translation handlers for six max/min MXU instructions.

Backports commit bb84cbf38505bd1d800fdddcd81407a99e5c2142 from qemu
2019-01-05 07:55:39 -05:00
Aleksandar Markovic bf7da7bf57
target/mips: MXU: Add handlers for logic instructions
Add translation handlers for four logic MXU instructions.

It should be noted that there is an error in MXU documentation (dated
June 2017) regarding opcodes for this group of instructions. This was
confirmed by running tests on hardware, and also by looking up other
related public source trees (binutils, Android NDK). In initial MXU
patches to QEMU, opcodes for MXU logic instructions were created to
be in accordance with the MXU documentation, therefore the error from
was propagated. This patch corrects that, changing the involved code.
Besides that, as MXU was designed and implemented only for 32-bit
CPUs, corresponding preprosessor conditions were added around MXU
code, which allows more flexible implementation of MXU handlers.

Backports commit b621f0187ef789aeef733cf79e5ac83984752394 from qemu
2019-01-05 07:48:08 -05:00
Aleksandar Markovic ba253dd0d3
target/mips: MXU: Improve the comment containing MXU overview
Improve textual description of MXU extension. These are mostly
comment formatting changes.

Backports commit 84e2c895b12fb7056daeb7e5094656eae7b50d3d from qemu
2019-01-05 07:39:47 -05:00
Aleksandar Markovic 57bb979ce8
target/mips: MXU: Add generic naming for optn2 constants
Add generic naming involving generig suffixes OPTN0, OPTN1, OPTN2,
OPTN3 for four optn2 constants. Existing suffixes WW, LW, HW, XW
are not quite appropriate for some instructions using optn2.
2019-01-05 07:35:49 -05:00
Aleksandar Markovic b5e1ea2e08
target/mips: MXU: Add missing opcodes/decoding for LX* instructions
Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
and LXHU instructions. They were for some reason forgotten in
previous commits. The MXU opcode list and decoding engine should
be now complete.

Backports commit c233bf07af7cf2358b69c38150dbd2e3e4a399b6 from qemu
2019-01-05 07:34:07 -05:00
Aleksandar Markovic d1f2d2c57b
target/mips: Disable R5900 support
Disable R5900 support. There are some outstanding issues related
to ABI support and emulation accuracy, that were not understood
well during review process. Disable to avoid backward compatibility
issues.

Reverts commit ed4f49ba9bb56ebca6987b1083255daf6c89b5de.

Backports commit 823f2897bdd78185f3ba33292a25105ba8bad1b5 from qemu
2018-11-23 18:55:12 -05:00
Aleksandar Markovic 3b89ca7188
target/mips: Rename MMI-related functions
Rename MMI-related functions.

Backports commit 874b28797045f574adb10b69c28006ca143f9280 from qemu
2018-11-23 18:54:02 -05:00
Aleksandar Markovic f51b980772
target/mips: Rename MMI-related opcodes
Rename MMI-related opcodes.

Backports commit baa609db75057b6a84c1867049e85d553b990090 from qemu
2018-11-23 18:49:13 -05:00
Aleksandar Markovic 8f8c6e3bb5
target/mips: Rename MMI-related masks
Rename MMI-related masks.

Backports commit c8341e00007f51e777b8b00b3fc3f475b3684001 from qemu
2018-11-23 18:41:55 -05:00
Fredrik Noring ed586cfa46
target/mips: Guard check_insn with INSN_R5900 check
Explicitely mark handling of PREF instruction for R5900 as
treating the same as NOP.

Backports commit 992e8176d36882983bb04f0259f7151a36d003a1 from qemu
2018-11-23 18:39:37 -05:00
Fredrik Noring a79d4b6fe7
target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
Avoid using check_opc_user_only() as a decision making code wrt
various architectures. Use ctx->insn_flags checks instead.

Backports commit 55fc7a69aa38f5ec726e862caf4e4394caca04a8 from qemu
2018-11-23 18:38:08 -05:00
Fredrik Noring b671293fe0
target/mips: Fix decoding mechanism of special R5900 opcodes
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.

Backports commit 9dc324ce66807cc231fe890d4031de595ad1cf72 from qemu
2018-11-23 18:35:55 -05:00
Fredrik Noring f23c6fd006
target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.

Backports commit c42171c3bfe6fdc94c183f664c4d6548f8c5488b from qemu
2018-11-23 18:33:35 -05:00
Fredrik Noring 3d637206bd
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.

Backports commit 86efbfb619a42061ac6439c074cfbf52df2ef2c2 from qemu
2018-11-23 18:29:01 -05:00
Aleksandar Markovic 9137e4c201
target/mips: Amend MXU ASE overview note
Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.

Backports commit 093ade12179b6a3f679c100c0fe2a0a7d72068ba from qemu
2018-11-11 07:30:31 -05:00
Aleksandar Markovic 702abac53f
target/mips: Move MXU_EN check one level higher
Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Backports commit e5bf8a08293a1c576f8b6094f4deae7bdafceade from qemu
2018-11-11 07:29:11 -05:00
Craig Janeczek f2c3e173ad
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Backports commit 4ca837218c92139cb85d214a25d1d1bc3f7e044c from qemu
2018-11-11 07:24:27 -05:00
Craig Janeczek bd75529f43
target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Backports commit a9a4181bdbf9eea81d718894bda607bd01b00f5b from qemu
2018-11-11 07:21:44 -05:00
Craig Janeczek 97b7155db1
target/mips: Add emulation of MXU instruction D16MAC
Backports commit e67915b4277932def37b15cf8434323d096edeaa from qemu
2018-11-11 07:18:12 -05:00
Craig Janeczek db2e8c1761
target/mips: Add emulation of MXU instruction D16MUL
Backports commit 72c9bcf89c59ee1a8e4545069de3efcbeb4d4833 from qemu
2018-11-11 07:00:00 -05:00
Craig Janeczek cad0283888
target/mips: Add emulation of MXU instruction S8LDD
Backports commit be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6 from qemu
2018-11-11 06:15:57 -05:00
Aleksandar Markovic 914c0cea7c
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Backports commit 87860df5511b972f0234a6b2cfaad5227c79b6b4 from qemu
2018-11-11 06:12:44 -05:00
Craig Janeczek 3862cd205d
target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.

Backports commit 96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b from qemu
2018-11-11 06:11:09 -05:00
Craig Janeczek 8a03757fb0
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Backports commit 11d56f61036091206f085e58cff72b6872911d3a from qemu
2018-11-11 06:05:45 -05:00
Craig Janeczek 839f5babde
target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Backports commit 53f1131fde02ae49e1f794f811a60fda32c72dca from qemu
2018-11-11 06:04:47 -05:00
Craig Janeczek bc98daa7c5
target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Backports commit a35723f4ce026ebad0c34f18ea874813799058f0 from qemu
2018-11-11 06:04:18 -05:00
Aleksandar Markovic 9cf4a32b0d
target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Backports commit 5bb29992397217ae7d09d2192c5b56aefaf6cd11 from qemu
2018-11-11 06:03:47 -05:00
Craig Janeczek bbb2a1e62b
target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Backports commit b70bb918e2f5063975ba845fb9456ada25e3db91 from qemu
2018-11-11 06:03:08 -05:00
Aleksandar Markovic 5e92fd655f
target/mips: Add MXU decoding engine
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.

Backports commit 03f400883a1dd92fac5b0d9127b38e34c9a722d7 from qemu
2018-11-11 06:01:58 -05:00
Aleksandar Markovic 1029b4151d
target/mips: Add and integrate MXU decoding engine placeholder
Provide the placeholder and add the invocation logic for MXU
decoding engine.

Backports commit 0a348b9a4e115deb28856e650b8fe5277e291c23 from qemu
2018-11-11 05:59:20 -05:00
Aleksandar Markovic ed037799c7
target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.

Backports commit eab0bdb07cbed1131be2d1f541059c7b96b05e32 from qemu
2018-11-11 05:58:35 -05:00
Craig Janeczek 8429d98b40
target/mips: Define a bit for MXU in insn_flags
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Backports commit a031ac61619294ae473a78d1834e757fad8b59e5 from qemu
2018-11-11 05:52:18 -05:00
Craig Janeczek 58dc377890
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
2018-11-11 05:50:52 -05:00
Aleksandar Markovic a1ba04ae44
target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Coverity found two fallthroughs that miss break statement. Fix them.

Backports commit 2431a422d325c1832d77dd64fa3135ec303b00de from qemu
2018-11-11 05:44:23 -05:00
Dimitrije Nikolic 948d49db81
target/mips: Implement emulation of nanoMIPS EVA instructions
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.

Backports commit d046a9ea1b8877a570a8b12a2d0125ec59fe5b22 from qemu
2018-11-10 12:18:11 -05:00
Aleksandar Markovic 006f0a5873
target/mips: Add nanoMIPS CRC32 instruction pool
Backports commit ba1e81171fb761aea9a9a4ccadedf808e34eaae2 from qemu
2018-11-10 12:15:01 -05:00
Aleksandar Markovic 9f728678ec
target/mips: Fix decoding of ALIGN and DALIGN instructions
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.

Backports commit 373ecd3823f949fd550ec49685299e287af5753e from qemu
2018-11-10 12:14:01 -05:00
Aleksandar Markovic caa67a9d17
target/mips: Fix the title of translate.c
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.

Backports commit ab99e0e44bc7b0e2e52d9083a673866b18470536 from qemu
2018-11-10 12:12:27 -05:00
Fredrik Noring a93e15aad1
target/mips: Define the R5900 CPU
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo.

GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
only emits two instructions that are specific to the R5900: the three-
operand MULT and MULTU. GCC and libc also emit certain MIPS III
instructions that are not part of the R5900 ISA. They are normally
trapped and emulated by the Linux kernel, and therefore need to be
treated accordingly by QEMU.

A program compiled by GCC is taken to mean source code compiled by GCC
under the restrictions above. One can, with the apparent limitations,
with a bit of effort obtain a fully functioning operating system such
as R5900 Gentoo. Strictly speaking, programs need not be compiled by
GCC to make use of this change.

Instructions and other facilities of the R5900 not implemented by this
change are intended to signal provisional exceptions. One such example
is the FPU that is not compliant with IEEE 754-1985 in system mode. It
is therefore provisionally disabled. In user space the FPU is trapped
and emulated by IEEE 754-1985 compliant software in the kernel, and
this is handled accordingly by QEMU. Another example is the 93
multimedia instructions specific to the R5900 that generate provisional
reserved instruction exception signals.

One of the benefits of running a Linux distribution under QEMU is that
programs can be compiled with a native compiler, where the host and
target are the same, as opposed to a cross-compiler, where they are
not the same. This is especially important in cases where the target
hardware does not have the resources to run a native compiler.

Problems with cross-compilation are often related to host and target
differences in integer sizes, pointer sizes, endianness, machine code,
ABI, etc. Sometimes cross-compilation is not even supported by the
build script for a given package. One effective way to avoid those
problems is to replace the cross-compiler with a native compiler. This
change of compilation methods does not resolve the inherent problems
with cross-compilation.

The native compiler naturally replaces the cross-compiler, because one
typically uses one or the other, and preferably the native compiler
when the circumstances admit this. The native compiler is also a good
test case for the R5900 QEMU user mode. Additionally, Gentoo is well-
known for compiling and installing its packages from sources.

This change has been tested with Gentoo compiled for R5900, including
native compilation of several packages under QEMU.

Backports commit ed4f49ba9bb56ebca6987b1083255daf6c89b5de from qemu.
2018-11-10 12:11:11 -05:00
Fredrik Noring e9a4475a35
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.

This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.

The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.

Backports commit 96631327be14c4f54cc31f873c278d9ffedd1e00 from qemu
2018-11-10 12:10:01 -05:00
Fredrik Noring cb7b097204
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.

Backports commit 5601e6217d90ed322b4b9a6d68e8db607db91842 from qemu
2018-11-10 12:08:14 -05:00
Fredrik Noring 296d8bd729
target/mips: Support R5900 DIV1 and DIVU1 instructions
Backports commit be9c42c90d162100a63111ddeb8bfe50be897873 from qemu
2018-11-10 12:07:24 -05:00
Fredrik Noring b42c8e80b8
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Backports commit 8d927f7cb4b3ec06d6a7cf71221fd6a48e9a8fb5 from qemu
2018-11-10 12:06:20 -05:00
Fredrik Noring 3914d65fb9
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
Add support for MULT1 and MULTU1 instructions.

Backports commit 06de726b2d4da185dfec9d06b5f1032059ad3554 from qemu
2018-11-10 12:04:28 -05:00
Fredrik Noring 91cd7c20e5
target/mips: Support R5900 three-operand MULT and MULTU instructions
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.

Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.

Backports commit 21e8e8b230af38b6bd8c953fa5f31e4a5a128e1c from qemu
2018-11-10 11:57:54 -05:00
Fredrik Noring 7da9860cf5
target/mips: Add a placeholder for R5900 MMI3 instruction subclass
Add a placeholder for MMI3 subclass.

Backports commit ec1944fc8eb862d48a0c74671105ce13acbc9c9e from qemu
2018-11-10 11:54:48 -05:00
Fredrik Noring 13d02e9aad
target/mips: Add a placeholder for R5900 MMI2 instruction subclass
Backports commit 6c1e48d38a2d26cca2d2b00f331a4ac7dbfae3ca from qemu
2018-11-10 11:52:47 -05:00
Fredrik Noring 63d9f0c6b7
target/mips: Add a placeholder for R5900 MMI1 instruction subclass
Backports commit 7a803ca23a6d6ac0d1d34469cd3f010a66cd381a from qemu
2018-11-10 11:51:47 -05:00
Fredrik Noring 685ccc52e7
target/mips: Add a placeholder for R5900 MMI0 instruction subclass
Add a placeholder for MMI0 subclass.

Backports commit 88eafe0b28c8e88ed6d38eb27dbf482f9c885745 from qemu
2018-11-10 11:50:48 -05:00
Fredrik Noring e71d43fd8d
target/mips: Add a placeholder for R5900 MMI instruction class
Add a placeholder for MMI class. This is the main palceholder for
MMI ASE.

backports commit 71b8a6b3f3d89283b094e04962c077aa01401438 from qemu
2018-11-10 11:49:19 -05:00
Fredrik Noring 496fe3ba14
target/mips: Add a placeholder for R5900 LQ
Add a placeholder for LQ instruction.

Backports commit f08099ad7a4dd32e12a3f9d4b4b04c32d7522b03 from qemu
2018-11-10 11:41:10 -05:00
Fredrik Noring cfc33249ce
target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR
Add placeholder for SQ instruction, handle RDHWR.

Backports commit bb41e74b66a8879ba5c23db145039faa27df5766 from qemu
2018-11-10 11:40:18 -05:00
Fredrik Noring 32a644a4a1
target/mips: Bunch of opcodes
Globs a bunch of MIPS commits together from qemu.
2018-11-10 11:39:20 -05:00
Fredrik Noring 5a6b86a346
target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
Define MMI class, LQ, and SQ R5900 opdoces.

Backports commit f99c0d6da3424dd48ad1f0345464f63515949be6 from qemu
2018-11-10 11:32:27 -05:00
Fredrik Noring fa90149289
target/mips: Add R5900 Multimedia Instruction overview note
Add a comment on R5900 MMI ASE (short overview).

Backports commit 497f072b159effc4b19d9629e4818e6185be5776 from qemu
2018-11-10 11:30:57 -05:00
Fredrik Noring 93fb8273c8
target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants
The R5900 implements the 64-bit MIPS III instruction set except
DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV
instructions MOVN, MOVZ and PREF are implemented. It has the
R5900-specific three-operand instructions MADD, MADDU, MULT and
MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1,
MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit
multimedia instructions specific to the R5900 is also implemented.

The Toshiba TX System RISC TX79 Core Architecture manual:

https://wiki.qemu.org/File:C790.pdf

describes the C790 processor that is a follow-up to the R5900. There
are a few notable differences in that the R5900 FPU

- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.

Backports commit 6f692818a7b53630702d25a709cd61282fd139ad from qemu
2018-11-10 11:29:25 -05:00
Dimitrije Nikolic 856974c7b2
target/mips: Add opcodes for nanoMIPS EVA instructions
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.

Backports commit 0d30b3bbc5fed12da8f8d1bfd28f2803d65a4cb0 from qemu
2018-10-23 14:33:08 -04:00
Stefan Markovic c3541a4b48
target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).

Backports commit d5ebcbaf09e8c14e62b2966446195be5eeabcbab from qemu
2018-10-23 14:32:22 -04:00
Matthew Fortune 255ced3c1a
target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions.
Their handling was permuted.

Backports commit fdac60cd0458f34b2e79d74a55bec10836e26471 from qemu
2018-10-23 14:31:26 -04:00
Yongbok Kim 73c2955d2b
target/mips: Implement hardware page table walker for MIPS32
Implement hardware page table walker. This implementation is
limiter only to MIPS32.

Backports commit 074cfcb4daedf59ccbbbc83c24eee80e0e8f4c71 from qemu
2018-10-23 14:29:27 -04:00
Yongbok Kim e1ea411300
target/mips: Add reset state for PWSize and PWField registers
Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa

Backports commit 630107955757b9dfc5c09f105caa267eded2e3b1 from qemu
2018-10-23 14:23:59 -04:00
Yongbok Kim a35a59bda6
target/mips: Add CP0 PWCtl register
Add PWCtl register (CP0 Register 5, Select 6).

The PWCtl register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

PWEn (31) - Hardware Page Table walker enable
PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only)
XK (28) - If 1, walker handles xkseg (MIPS64 only)
XS (27) - If 1, walker handles xsseg (MIPS64 only)
XU (26) - If 1, walker handles xuseg (MIPS64 only)
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE

Backports commit 103be64c26c166f12b3e1308edadef3443723ff1 from qemu
2018-10-23 14:23:04 -04:00
Yongbok Kim a5194f6dfc
target/mips: Add CP0 PWSize register
Add PWSize register (CP0 Register 5, Select 7).

The PWSize register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

BDW (37..32) Base Directory index width (MIPS64 only)
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index

Backports commit 20b28ebc49945583d7191b57755cfd92433de9ff from qemu
2018-10-23 14:08:55 -04:00
Yongbok Kim 0597704314
target/mips: Add CP0 PWField register
Add PWField register (CP0 Register 5, Select 6).

The PWField register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

MIPS64:
BDI (37..32) - Base Directory index
GDI (29..24) - Global Directory index
UDI (23..18) - Upper Directory index
MDI (17..12) - Middle Directory index
PTI (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift

MIPS32:
GDW (29..24) - Global Directory index
UDW (23..18) - Upper Directory index
MDW (17..12) - Middle Directory index
PTW (11..6 ) - Page Table index
PTEW ( 5..0 ) - Page Table Entry shift

Backports commit fa75ad1459f4f6abbeb6d375a812dfad61320f58 from qemu
2018-10-23 13:52:31 -04:00
Yongbok Kim 2414d1fe05
target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5).

The PWBase register contains the Page Table Base virtual address.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.

Backports commit 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6 from qemu
2018-10-23 13:47:49 -04:00
Stefan Markovic 06cb2b1420
target/mips: Add CP0 Config2 to DisasContext
Add field corresponding to CP0 Config2 to DisasContext. This is
needed for availability control via Config2 bits.

Backports commit 49735f76db25bf10f57973d5249f17151b801760 from qemu
2018-10-23 13:43:02 -04:00
Stefan Markovic 64bec62433
target/mips: Improve DSP R2/R3-related naming
Do following replacements:

ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2
MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()

and several other similar minor replacements.

Backports commit 908f6be1b9cbc270470230f805d6f7474ab3178d from qemu
2018-10-23 13:42:01 -04:00
Stefan Markovic 6dd29739a9
target/mips: Add availability control for DSP R3 ASE
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.

Backports commit 59e781fbf13a2dede15437d055b09d7ea120dcac from qemu
2018-10-23 13:36:07 -04:00
Stefan Markovic 071fe91d6a
target/mips: Add bit definitions for DSP R3 ASE
Add DSP R3 ASE related bit definition for insn_flags and hflags.

Backports commit 6208f09441dcf8d142ff0e1624ef12da298776a4 from qemu
2018-10-23 13:19:18 -04:00
Philippe Mathieu-Daudé 2a27a61c51
target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
Distribute bits 56-63 vendor-specific ASEs as follows:

- bits 0-31 MIPS base instruction sets
- bits 32-47 MIPS ASEs
- bits 48-55 vendor-specific base instruction sets
- bits 56-63 vendor-specific ASEs

Backports commit 45ebdd24c3de158890ce390df39855a891e80701 from qemu
2018-10-23 13:18:11 -04:00
Philippe Mathieu-Daudé 055b2e4bdc
target/mips: Increase 'supported ISAs/ASEs' flag holder size
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.

Backports commit f9c9cd63e3dd84c5f052deec880ec92046bbe305 from qemu
2018-10-23 13:17:08 -04:00
Aleksandar Markovic e52c27e21c
target/mips: Add opcode values of MXU ASE
Add opcode values for all instructions in MXU ASE.

Backports commit 8bacd1ffc702c35d34ccd29b1a20c0273c9759cb from qemu
2018-10-23 13:15:43 -04:00
Aleksandar Markovic b6c9c13c4e
target/mips: Add organizational chart of MXU ASE
Add a comment that contains an organizational chart of MXU ASE
instructions.

Backports commit 9ef5bff97b0d033e20446c83fc61bae7c054b03e from qemu
2018-10-23 13:14:52 -04:00
Aleksandar Markovic 120b8c24b4
target/mips: Add assembler mnemonics list for MXU ASE
Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.

Backports commit 1d0e663c5f25345a6702d8a83c051b83f3462299 from qemu
2018-10-23 13:13:34 -04:00
Aleksandar Markovic 96d299bd6f
target/mips: Add basic description of MXU ASE
Add a comment that contains a basic description of MXU ASE.

Backports commit b158d449bbfe71bb203fdce978a4a33c38a4e821 from qemu
2018-10-23 13:12:35 -04:00
Aleksandar Markovic 2cf0f05c27
target/mips: Add a comment before each CP0 register section in cpu.h
Add a comment before each CP0 register section in CPUMIPSState
definition, thus visually separating these sections.

Backports commit 50e7edc5ac25af2faaacd1f91e177c7de7d696c3 from qemu
2018-10-23 13:12:04 -04:00
Aleksandar Markovic d9ae47e2da
target/mips: Add a comment with an overview of CP0 registers
Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.

Backports commit a86d421e18d58b32d6eaba1e79160e2b4e5a0a6c from qemu
2018-10-23 13:06:39 -04:00
Catena cyber 2c9b6df879
Mips undefined shift fix
Backports commit 46999575fb9e82ccd925e835d0d7db47200e010d from unicorn
2018-10-06 05:00:27 -04:00
Lioncash b62e892b20
mips: Use DisasContext for parameters in place of TCGContext where applicable
This is more future-friendly with qemu's main repo, as it's more
generic.
2018-10-06 04:37:28 -04:00
Lioncash fa8f566635
target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:36:23 -04:00
Stefan Markovic c870339a10
target/mips: Add definition of nanoMIPS I7200 CPU
Add definition of the first nanoMIPS processor in QEMU.

Backports commit d45942d908edee175a90f915ab92ac302eedf33a from qemu
2018-08-27 15:08:12 -04:00
Yongbok Kim d53c021cea
target/mips: Fix ERET/ERETNC behavior related to ADEL exception
Fix ERET/ERETNC so that ADEL exception can be raised.

Backports commit 26324ded91a5ad08a5de8f32b8ed5e5e243154cf from qemu
2018-08-27 15:00:59 -04:00
Stefan Markovic 7473e6dbe6
target/mips: Add updating BadInstr and BadInstrX for nanoMIPS
Update BadInstr and BadInstrX registers for nanoMIPS. The same
support for pre-nanoMIPS remains unimplemented.

Backports commit 7a5f784aa215df6bf5d674b4003f8df43bf3b2d4 from qemu
2018-08-27 15:00:05 -04:00
Dimitrije Nikolic 7e0342c9f6
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS
is set.

Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
2018-08-27 14:59:15 -04:00
Stefan Markovic 38f2640a34
target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Backports commit 0b591184a2d0686b8f2c5fb27cc9fe2f60752d57 from qemu
2018-08-27 06:47:59 -04:00
Stefan Markovic ba7d8bc0ab
target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Backports commit 4c75c985d9b4d2ac7e0183083e31c243b06a3f2b from qemu
2018-08-27 06:45:25 -04:00
Stefan Markovic 73a5efd599
target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
2018-08-27 06:43:34 -04:00
Stefan Markovic b6602fff1f
target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
Add emulation of DSP ASE instructions for nanoMIPS - part 3.

Backports commit 2ed42efaae9516b71b7edf669b120cad718ba37b from qemu
2018-08-27 06:34:14 -04:00
Stefan Markovic 33dee2e5f3
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Backports commit 6d033ca7513d85562f1b6bbb002a38b1c2541e5d from qemu
2018-08-27 05:53:17 -04:00
Stefan Markovic 49f448af3c
target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
Add emulation of DSP ASE instructions for nanoMIPS - part 1.

Backports commit 3285a3e4445be70d5f2dbdd29249e1e2627a5216 from qemu
2018-08-27 05:52:12 -04:00
Stefan Markovic 795d903f1c
target/mips: Implement MT ASE support for nanoMIPS
Add emulation of MT ASE instructions for nanoMIPS.

Backports commit 0a1a6ed78ae13a87f23810899a838f8d0c0fa2a5 from qemu
2018-08-27 05:39:15 -04:00