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3608 commits

Author SHA1 Message Date
Aaron Lindsay e1d021ad74
target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
They share the same underlying state

Backports commit 169c893874977eee8303a6dad4a3f25c5464858f from qemu
2018-04-26 09:07:50 -04:00
Aaron Lindsay e1bffbf7df
target/arm: Check PMCNTEN for whether PMCCNTR is enabled
Backports commit ccbc0e338486b21cb0eb52e52cd309bbbe6a7507 from qemu
2018-04-26 09:07:02 -04:00
Peter Maydell 43e7478d3f
target/arm: Use v7m_stack_read() for reading the frame signature
In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack
pop code to use a new v7m_stack_read() function that checks
whether the read should fail due to an MPU or bus abort.
We missed one call though, the one which reads the signature
word for the callee-saved register part of the frame.

Correct the omission.

Backports commit 4818bad98c8212fbbb0525d10761b6b65279ab92 from qemu
2018-04-26 09:02:11 -04:00
Peter Maydell bec50934ad
target/arm: Remove stale TODO comment
Remove a stale TODO comment -- we have now made the arm_ldl_ptw()
and arm_ldq_ptw() functions propagate physical memory read errors
out to their callers.

Backports commit 145772707fe80395b87c244ccf5699a756f1946b from qemu
2018-04-26 09:00:08 -04:00
Richard Henderson 76e343ef55
fpu: Bound increment for scalbn
Without bounding the increment, we can overflow exp either here
in scalbn_decomposed or when adding the bias in round_canonical.
This can result in e.g. underflowing to 0 instead of overflowing
to infinity.

The old softfloat code did bound the increment.

Backports commit ce8d4082054519f2eaac39958edde502860a7fc6 from qemu
2018-04-18 09:21:03 -04:00
Alex Bennée af6a0b7c14
fpu/softfloat: check for Inf / x or 0 / x before /0
The re-factoring of div_floats changed the order of checking meaning
an operation like -inf/0 erroneously raises the divbyzero flag.
IEEE-754 (2008) specifies this should only occur for operations on
finite operands.

We fix this by moving the check on the dividend being Inf/0 to before
the divisor is zero check.

Backports commit 9cb4e398c2f95c1e837fe9c570e124a55259f725 from qemu
2018-04-18 09:19:28 -04:00
Pavel Dovgalyuk fe353764e9
m68k: fix exception stack frame for 68000
68000 CPUs do not save format in the exception stack frame.
This patch adds feature checking to prevent format saving for 68000.
m68k_ret() already includes this modification, this patch fixes
the exception processing function too.

Backports commit 000761dc0c97d70e7314db3e8f52783880325a22 from qemu
2018-04-16 13:49:56 -04:00
Alex Bennée 9517a002da
fpu/softfloat: raise float_invalid for NaN/Inf in round_to_int_and_pack
The re-factor broke the raising of INVALID when NaN/Inf is passed to
the float_to_int conversion functions. round_to_uint_and_pack got this
right for NaN but also missed out the Inf handling.

Fixes https://bugs.launchpad.net/qemu/+bug/1759264

Backports commit 801bc56336a127d9b351b3a2cc0336e4d0cb2686 from qemu
2018-04-16 13:48:17 -04:00
Emilio G. Cota 74b7fe484c
softfloat: fix {min, max}nummag for same-abs-value inputs
Before 8936006 ("fpu/softfloat: re-factor minmax", 2018-02-21),
we used to return +Zero for maxnummag(-Zero,+Zero); after that
commit, we return -Zero.

Fix it by making {min,max}nummag consistent with {min,max}num,
deferring to the latter when the absolute value of the operands
is the same.

With this fix we now pass fp-test.

Backports commit 6245327a367292b354489c54e965646823023919 from qemu
2018-04-16 13:46:29 -04:00
Peter Maydell 778d0c47df
tcg/mips: Handle large offsets from target env to tlb_table
The MIPS TCG target makes the assumption that the offset from the
target env pointer to the tlb_table is less than about 64K. This
used to be true, but gradual addition of features to the Arm
target means that it's no longer true there. This results in
the build-time assertion failing:

In file included from /home/pm215/qemu/include/qemu/osdep.h:36:0,
from /home/pm215/qemu/tcg/tcg.c:28:
/home/pm215/qemu/tcg/mips/tcg-target.inc.c: In function ‘tcg_out_tlb_load’:
/home/pm215/qemu/include/qemu/compiler.h:90:36: error: static assertion failed: "not expecting: offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) > 0x7ff0 + 0x7fff"
^
/home/pm215/qemu/include/qemu/compiler.h:98:30: note: in expansion of macro ‘QEMU_BUILD_BUG_MSG’
^
/home/pm215/qemu/tcg/mips/tcg-target.inc.c:1236:9: note: in expansion of macro ‘QEMU_BUILD_BUG_ON’
QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
^
/home/pm215/qemu/rules.mak:66: recipe for target 'tcg/tcg.o' failed

An ideal long term approach would be to rearrange the CPU state
so that the tlb_table was not so far along it, but this is tricky
because it would move it from the "not cleared on CPU reset" part
of the struct to the "cleared on CPU reset" part. As a simple fix
for the 2.12 release, make the MIPS TCG target handle an arbitrary
offset by emitting more add instructions. This will mean an extra
instruction in the fastpath for TCG loads and stores for the
affected guests (currently just aarch64-softmmu)

Backports commit 161dfd1e7fad1203840c0390f235030eba3fd23c from qemu
2018-04-16 13:44:39 -04:00
Pavel Dovgalyuk b4bf3c776b
icount: fix cpu_restore_state_from_tb for non-tb-exit cases
In icount mode, instructions that access io memory spaces in the middle
of the translation block invoke TB recompilation. After recompilation,
such instructions become last in the TB and are allowed to access io
memory spaces.

When the code includes instruction like i386 'xchg eax, 0xffffd080'
which accesses APIC, QEMU goes into an infinite loop of the recompilation.

This instruction includes two memory accesses - one read and one write.
After the first access, APIC calls cpu_report_tpr_access, which restores
the CPU state to get the current eip. But cpu_restore_state_from_tb
resets the cpu->can_do_io flag which makes the second memory access invalid.
Therefore the second memory access causes a recompilation of the block.
Then these operations repeat again and again.

This patch moves resetting cpu->can_do_io flag from
cpu_restore_state_from_tb to cpu_loop_exit* functions.

It also adds a parameter for cpu_restore_state which controls restoring
icount. There is no need to restore icount when we only query CPU state
without breaking the TB. Restoring it in such cases leads to the
incorrect flow of the virtual time.

In most cases new parameter is true (icount should be recalculated).
But there are two cases in i386 and openrisc when the CPU state is only
queried without the need to break the TB. This patch fixes both of
these cases.

Backports commit afd46fcad2dceffda35c0586f5723c127b6e09d8 from qemu
2018-04-11 20:05:40 -04:00
Alex Bennée 4074587775
accel/tcg/translate-all: expand cpu_restore_state addr check
We are still seeing signals during translation time when we walk over
a page protection boundary. This expands the check to ensure the host
PC is inside the code generation buffer. The original suggestion was
to check versus tcg_ctx.code_gen_ptr but as we now segment the
translation buffer we have to settle for just a general check for
being inside.

I've also fixed up the declaration to make it clear it can deal with
invalid addresses. A later patch will fix up the call sites.

Backports commit d25f2a72272b9ffe0d06710d6217d1169bc2cc7d from qemu
2018-04-11 19:53:57 -04:00
Richard Henderson bc8e85a1c5
fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
We incorrectly passed in the current rounding mode
instead of float_round_to_zero.

Backports commit bd49e6027cbc207c87633c7add3ebd7d3474cd35 from qemu
2018-04-11 19:36:12 -04:00
Richard Henderson 49476ebf5e
tcg: Introduce tcg_set_insn_start_param
The parameters for tcg_gen_insn_start are target_ulong, which may be split
into two TCGArg parameters for storage in the opcode on 32-bit hosts.

Fixes the ARM target and its direct use of tcg_set_insn_param, which would
set the wrong argument in the 64-on-32 case.

Backports commit 9743cd5736263e90d312b2c33bd739ffe1eae70d from qemu
2018-04-11 19:34:18 -04:00
Peter Maydell 8f26d8e556
target/arm: Report unsupported MPU region sizes more clearly
Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
report that in a slightly confusing way:

DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10

The problem is not the alignment of the region, but its size;
tweak the error message to say so:
DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024.

Backports commit 8aec759b45fa6986c0b159cb27353d6abb0d5d73 from qemu
2018-04-11 19:32:16 -04:00
Onur Sahin 18e6b1549f
target-arm: Check undefined opcodes for SWP in A32 decoder
Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.

Backports commit c4869ca630a57f4269bb932ec7f719cef5bc79b8 from qemu
2018-04-11 19:30:50 -04:00
Eugene Minibaev 87180dd231
Add missing bit for SSE instr in VEX decoding
The 2-byte VEX prefix imples a leading 0Fh opcode byte.

Backports commit e0014d4b3a955cfd8d517674703bfa87f340290a from qemu
2018-04-10 08:49:15 -04:00
Alexandro Sanchez Bach 4a1de154ef
target/i386: Fix andn instruction
In commit 7073fbada733c8d10992f00772c9b9299d740e9b, the `andn` instruction
was implemented via `tcg_gen_andc` but passes the operands in the wrong
order:
- X86 defines `andn dest,src1,src2` as: dest = ~src1 & src2
- TCG defines `andc dest,src1,src2` as: dest = src1 & ~src2

The following simple test shows the issue:

int main(void) {
uint32_t ret = 0;
__asm (
"mov $0xFF00, %%ecx\n"
"mov $0x0F0F, %%eax\n"
"andn %%ecx, %%eax, %%ecx\n"
"mov %%ecx, %0\n"
: "=r" (ret));
printf("%08X\n", ret);
return 0;
}

This patch fixes the problem by simply swapping the order of the two last
arguments in `tcg_gen_andc_tl`.

Backports commit 5cd10051c2e02b7a86eae49919d6c65a87dbea46 from qemu
2018-04-10 08:48:05 -04:00
Richard Henderson e0903adacf
tcg: Fix out-of-line generic vector compares
A mistake in the type passed to sizeof, that happens to work
when the out-of-line fallback itself is using host vectors,
but fails when using only the base types.

Backports commit 6cb1d3b8517572031a22675280ec642972cdb395 from qemu
2018-04-07 23:05:19 -04:00
Laurent Vivier b25de410a9
tcg: fix 16-byte vector operations detection
configure tries to detect if the compiler
supports 16-byte vector operations.

As stated in the comment of the detection
program, there is a problem with the system
compiler on GCC on Centos 7.

This program doesn't actually detect the problem
with GCC on RHEL7 on PPC64LE (Red Hat 4.8.5-28).

This patch updates the test to look more like
it is in QEMU helpers, and now detects the problem.

The error reported is:

CC ppc64-softmmu/accel/tcg/tcg-runtime-gvec.o
..//accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
../accel/tcg/tcg-runtime-gvec.c:558:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Fixes: db43267 "tcg: Add generic vector expanders"

Backports commit 74912f6dad207bfdd5bfa8c6012c364ea9405fc7 from qemu
2018-04-07 23:03:11 -04:00
Richard Henderson c2e46f2931
tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
Failure to do so results in the tcg optimizer sign-extending
any constant fold from 32-bits. This turns out to be visible
in the RISC-V testsuite using a host that emits these opcodes
(e.g. any non-x86_64).

Backports commit f2f1dde75160cac6ede330f3db50dc817d01a2d6 from qemu
2018-03-29 14:03:00 -04:00
Peter Maydell 92b5817d92
target/arm: Always set FAR to a known unknown value for debug exceptions
For debug exceptions due to breakpoints or the BKPT instruction which
are taken to AArch32, the Fault Address Register is architecturally
UNKNOWN. We were using that as license to simply not set
env->exception.vaddress, but this isn't correct, because it will
expose to the guest whatever old value was in that field when
arm_cpu_do_interrupt_aarch32() writes it to the guest IFSR. That old
value might be a FAR for a previous guest EL2 or secure exception, in
which case we shouldn't show it to an EL1 or non-secure exception
handler. It might also be a non-deterministic value, which is bad
for record-and-replay.

Clear env->exception.vaddress before taking breakpoint debug
exceptions, to avoid this minor information leak.

Backports commit 548f514cf89dd9ab39c0cb4c063097bccf141fdd from qemu
2018-03-25 16:38:14 -04:00
Peter Maydell d6eafe5982
target/arm: Set FSR for BKPT, BRK when raising exception
Now that we have a helper function specifically for the BRK and
BKPT instructions, we can set the exception.fsr there rather
than in arm_cpu_do_interrupt_aarch32(). This allows us to
use our new arm_debug_exception_fsr() helper.

In particular this fixes a bug where we were hardcoding the
short-form IFSR value, which is wrong if the target exception
level has LPAE enabled.

Fixes: https://bugs.launchpad.net/qemu/+bug/1756927

Backports commit 62b94f31d0df75187bb00684fc29e8639eacc0c5 from qemu
2018-03-25 16:36:51 -04:00
Peter Maydell 16c0c2d253
target/arm: Factor out code to calculate FSR for debug exceptions
When a debug exception is taken to AArch32, it appears as a Prefetch
Abort, and the Instruction Fault Status Register (IFSR) must be set.
The IFSR has two possible formats, depending on whether LPAE is in
use. Factor out the code in arm_debug_excp_handler() which picks
an FSR value into its own utility function, update it to use
arm_fi_to_lfsc() and arm_fi_to_sfsc() rather than hard-coded constants,
and use the correct condition to select long or short format.

In particular this fixes a bug where we could select the short
format because we're at EL0 and the EL1 translation regime is
not using LPAE, but then route the debug exception to EL2 because
of MDCR_EL2.TDE and hand EL2 the wrong format FSR.

Backports commit 81621d9ab8a0f07956e67850b15eebf6d6992eec from qemu
2018-03-25 16:35:27 -04:00
Peter Maydell 7a3ee5fd95
target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
The MDCR_EL2.TDE bit allows the exception level targeted by debug
exceptions to be set to EL2 for code executing at EL0. We handle
this in the arm_debug_target_el() function, but this is only used for
hardware breakpoint and watchpoint exceptions, not for the exception
generated when the guest executes an AArch32 BKPT or AArch64 BRK
instruction. We don't have enough information for a translate-time
equivalent of arm_debug_target_el(), so instead make BKPT and BRK
call a special purpose helper which can do the routing, rather than
the generic exception_with_syndrome helper.

Backports commit c900a2e62dd6dde11c8f5249b638caad05bb15be from qemu
2018-03-25 16:33:04 -04:00
Victor Kamensky ecd2ecb590
arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT
In OE project 4.15 linux kernel boot hang was observed under
single cpu aarch64 qemu. Kernel code was in a loop waiting for
vtimer arrival, spinning in TC generated blocks, while interrupt
was pending unprocessed. This happened because when qemu tried to
handle vtimer interrupt target had interrupts disabled, as
result flag indicating TCG exit, cpu->icount_decr.u16.high,
was cleared but arm_cpu_exec_interrupt function did not call
arm_cpu_do_interrupt to process interrupt. Later when target
reenabled interrupts, it happened without exit into main loop, so
following code that waited for result of interrupt execution
run in infinite loop.

To solve the problem instructions that operate on CPU sys state
(i.e enable/disable interrupt), and marked as DISAS_UPDATE,
should be considered as DISAS_EXIT variant, and should be
forced to exit back to main loop so qemu will have a chance
processing pending CPU state updates, including pending
interrupts.

This change brings consistency with how DISAS_UPDATE is treated
in aarch32 case.

Backports commit a75a52d62418dafe462be4fe30485501d1010bb9 from qemu
2018-03-25 16:27:27 -04:00
Lioncash 1c4c5a9403
softfloat-specialize: Perform comparison pass with qemu
Ensures code and formatting are similar
2018-03-21 13:27:59 -04:00
Lioncash ba874ef639
softfloat: Perform comparison pass with qemu
Ensure that the code and formatting are similar.
2018-03-21 13:26:09 -04:00
Lioncash 2dc6364de9
object: Add assert to ensure uc is not null 2018-03-21 12:47:44 -04:00
Lioncash a0c39b4996
translate-all: Fix missing #elif condition in alloc_code_gen_buffer 2018-03-21 12:46:03 -04:00
Lioncash b65302b377
qemu-thread-win32: Prevent null pointer dereference in win32_start_routine 2018-03-21 12:42:44 -04:00
Lioncash 43fe0c8a1c
memory: Protect against use-after-free 2018-03-21 09:40:33 -04:00
Bharata B Rao 309b85548f
cpu: Convert cpu_index into a bitmap
Currently CPUState::cpu_index is monotonically increasing and a newly
created CPU always gets the next higher index. The next available
index is calculated by counting the existing number of CPUs. This is
fine as long as we only add CPUs, but there are architectures which
are starting to support CPU removal, too. For an architecture like PowerPC
which derives its CPU identifier (device tree ID) from cpu_index, the
existing logic of generating cpu_index values causes problems.

With the currently proposed method of handling vCPU removal by parking
the vCPU fd in QEMU
(Ref: http://lists.gnu.org/archive/html/qemu-devel/2015-02/msg02604.html),
generating cpu_index this way will not work for PowerPC.

This patch changes the way cpu_index is handed out by maintaining
a bit map of the CPUs that tracks both addition and removal of CPUs.

The CPU bitmap allocation logic is part of cpu_exec_init(), which is
called by instance_init routines of various CPU targets. Newly added
cpu_exec_exit() API handles the deallocation part and this routine is
called from generic CPU instance_finalize.

Note: This new CPU enumeration is for !CONFIG_USER_ONLY only.
CONFIG_USER_ONLY continues to have the old enumeration logic.

Backports commit b7bca7333411bd19c449147e8202ae6b0e4a8e09 from qemu
2018-03-21 08:06:07 -04:00
Bharata B Rao e373c001fa
cpu: Add Error argument to cpu_exec_init()
Add an Error argument to cpu_exec_init() to let users collect the
error. This is in preparation to change the CPU enumeration logic
in cpu_exec_init(). With the new enumeration logic, cpu_exec_init()
can fail if cpu_index values corresponding to max_cpus have already
been handed out.

Since all current callers of cpu_exec_init() are from instance_init,
use error_abort Error argument to abort in case of an error.

Backports commit 5a790cc4b942e651fec7edc597c19b637fad5a76 from qemu
2018-03-21 07:50:33 -04:00
Laurent Vivier c133a7b306
target/m68k: add a mechanism to automatically free TCGv
SRC_EA() and gen_extend() can return either a temporary
TCGv or a memory allocated one. Mark them when they are
allocated, and free them automatically at end of the
instruction translation.

We want to free locally allocated TCGv to avoid
overflow in sequence like:

0xc00ae406: movel %fp@(-132),%fp@(-268)
0xc00ae40c: movel %fp@(-128),%fp@(-264)
0xc00ae412: movel %fp@(-20),%fp@(-212)
0xc00ae418: movel %fp@(-16),%fp@(-208)
0xc00ae41e: movel %fp@(-60),%fp@(-220)
0xc00ae424: movel %fp@(-56),%fp@(-216)
0xc00ae42a: movel %fp@(-124),%fp@(-252)
0xc00ae430: movel %fp@(-120),%fp@(-248)
0xc00ae436: movel %fp@(-12),%fp@(-260)
0xc00ae43c: movel %fp@(-8),%fp@(-256)
0xc00ae442: movel %fp@(-52),%fp@(-276)
0xc00ae448: movel %fp@(-48),%fp@(-272)
...

That can fill a lot of TCGv entries in a sequence,
especially since 15fa08f845 ("tcg: Dynamically allocate TCGOps")
we have no limit to fill the TCGOps cache and we can fill
the entire TCG variables array and overflow it.

Backports commit ecc207d2fc1d45fabb16c38742a6675a7ba56cbc from qemu
2018-03-20 14:32:04 -04:00
Luwei Kang 30d878a0ef
i386: Disable Intel PT if packets IP payloads have LIP values
Intel processor trace should be disabled when
CPUID.(EAX=14H,ECX=0H).ECX.[bit31] is set.
Generated packets which contain IP payloads will have LIP
values when this bit is set, or IP payloads will have RIP
values.
Currently, The information of CPUID 14H is constant to make
live migration safty and this bit is always 0 in guest even
if host support LIP values.
Guest sees the bit is 0 will expect IP payloads with RIP
values, but the host CPU will generate IP payloads with
LIP values if this bit is set in HW.
To make sure the value of IP payloads correctly, Intel PT
should be disabled when bit[31] is set.

Backports relevant parts of commit c078ca968c6c7cb62781c1843d840cb0f5c72781 from qemu
2018-03-20 14:25:40 -04:00
Igor Mammedov 415b11ee49
cpu: drop unnecessary NULL check and cpu_common_class_by_name()
both do nothing as for the first all callers
parse_cpu_model() and qmp_query_cpu_model_()
should provide non NULL value, so just abort if it's not so.

While at it drop cpu_common_class_by_name() which is not need
any more as every target has CPUClass::class_by_name callback
by now, though abort in case a new arch will forget to define one.

Backports commit 99193d8f2ef594648ad67cc3d007b0e4fb2f8cf8 from qemu
2018-03-20 14:23:52 -04:00
Igor Mammedov cd27da0d88
cpu: get rid of unused cpu_init() defines
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so
no users are left, remove it.

Backports commit 3f71e724e283233753f1b5b3d6a30948d3084636 from qemu
2018-03-20 14:21:45 -04:00
Igor Mammedov f8eeacb280
Use cpu_create(type) instead of cpu_init(cpu_model)
With all targets defining CPU_RESOLVING_TYPE, refactor
cpu_parse_cpu_model(type, cpu_model) to parse_cpu_model(cpu_model)
so that callers won't have to know internal resolving cpu
type. Place it in exec.c so it could be called from both
target independed vl.c and *-user/main.c.

That allows us to stop abusing cpu type from
MachineClass::default_cpu_type
as resolver class in vl.c which were confusing part of
cpu_parse_cpu_model().

Also with new parse_cpu_model(), the last users of cpu_init()
in null-machine.c and bsd/linux-user targets could be switched
to cpu_create() API and cpu_init() API will be removed by
follow up patch.

With no longer users left remove MachineState::cpu_model field,
new code should use MachineState::cpu_type instead and
leave cpu_model parsing to generic code in vl.c.

Backports commit 2278b93941d42c30e2950d4b8dff4943d064e7de from qemu
2018-03-20 14:20:30 -04:00
Igor Mammedov 7fe1504224
arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
there are 2 use cases to deal with:
1: fixed CPU models per board/soc
2: boards with user configurable cpu_model and fallback to
default cpu_model if user hasn't specified one explicitly

For the 1st
drop intermediate cpu_model parsing and use const cpu type
directly, which replaces:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
object_new(typename)
with
object_new(FOO_CPU_TYPE_NAME)
or
cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
with
cpu_create(FOO_CPU_TYPE_NAME)

as result 1st use case doesn't have to invoke not necessary
translation and not needed code is removed.

For the 2nd
1: set default cpu type with MachineClass::default_cpu_type and
2: use generic cpu_model parsing that done before machine_init()
is run and:
2.1: drop custom cpu_model parsing where pattern is:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
[parse_features(typename, cpu_model, &err) ]

2.2: or replace cpu_generic_init() which does what
2.1 does + create_cpu(typename) with just
create_cpu(machine->cpu_type)
as result cpu_name -> cpu_type translation is done using
generic machine code one including parsing optional features
if supported/present (removes a bunch of duplicated cpu_model
parsing code) and default cpu type is defined in an uniform way
within machine_class_init callbacks instead of adhoc places
in boadr's machine_init code.

Backports commit ba1ba5cca3962a9cc400c713c736b4fb8db1f38e from qemu
2018-03-20 13:35:33 -04:00
Igor Mammedov 20f67e8f9a
pc: use generic cpu_model parsing
define default CPU type in generic way in pc_machine_class_init()
and let common machine code to handle cpu_model parsing

Patch also introduces TARGET_DEFAULT_CPU_TYPE define for 2 purposes:
* make foo_machine_class_init() look uniform on every target
* use define in [bsd|linux]-user targets to pick default
cpu type

Backports commit 311ca98d16bbb6a2a38b38ba898baa4a4d4ab9a7 from qemu
2018-03-20 13:22:05 -04:00
Igor Mammedov 733d60e6d7
vl.c: convert cpu_model to cpu type and set of global properties before machine_init()
All machines that support user specified cpu_model either call
cpu_generic_init() or cpu_class_by_name()/CPUClass::parse_features
to parse feature string and to get CPU type to create.

Which leads to code duplication and hard-codding default CPU model
within machine_foo_init() code. Which makes it impossible to
get CPU type before machine_init() is run.

So instead of setting default CPUs models and doing parsing in
target specific machine_foo_init() in various ways, provide
a generic data driven cpu_model parsing before machine_init()
is called.

in follow up per target patches, it will allow to:
* define default CPU type in consistent/generic manner
per machine type and drop custom code that fallbacks
to default if cpu_model is NULL
* drop custom features parsing in targets and do it
in centralized way.
* for cases of
cpu_generic_init(TYPE_BASE/DEFAULT_CPU, "some_cpu")
replace it with
cpu_create(machine->cpu_type) || cpu_create(TYPE_FOO)
depending if CPU type is user settable or not.
not doing useless parsing and clearly documenting where
CPU model is user settable or fixed one.

Patch allows machine subclasses to define default CPU type
per machine class at class_init() time and if that is set
generic code will parse cpu_model into a MachineState::cpu_type
which will be used to create CPUs for that machine instance
and allows gradual per board conversion.

Backports commit 6063d4c0f98b35a27ca018393d328a1825412a7e from qemu
2018-03-20 13:15:21 -04:00
Igor Mammedov 555eeb4120
qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts
it would allow to reuse feature parsing part in various machines
that have CPU features instead of re-implementing the same feature
parsing each time.

Backports commit 3c72234c98004a01d79a24f78b07053cfebd0f22 from qemu
2018-03-20 13:09:04 -04:00
Igor Mammedov cdc86cee50
qom: cpu: fix parsed feature string length
since commit ( 9262685 cpu: Factor out cpu_generic_init() )
features parsed by it were truncated only to the 1st feature
after CPU name due to fact that

   featurestr = strtok(NULL, ",");
   cc->parse_features(cpu, featurestr, &err);

would extract exactly one feature and parse_features() callback
would parse it and only it leaving the rest of features ignored.

Reuse approach from x86 custom impl. i.e. replace strtok() token
parsing with g_strsplit(), which would split feature string in
2 parts name and features list and pass the later to
parse_features() callback.

Backports commit 3e2cf187eb3954fc406f81247a3fa598437ce1de from qemu
2018-03-20 13:05:10 -04:00
Igor Mammedov 9c5153270f
i386: keep cpu_model field in MachineState uptodate
Considering that features are converted to global properties and
global properties are automatically applied to every new instance
of created CPU (at object_new() time), there is no point in
parsing cpu_model string every time a CPU created. So move
parsing outside CPU creation loop and do it only once.

Parsing also should be done before any CPU is created so that
features would affect the first CPU a well.

Backports commit 6aff24c6a61c6fec31e555c7748ba6085b7b2c06 from qemu
2018-03-20 12:40:35 -04:00
Igor Mammedov 8344a5a63c
pc: Parse CPU features only once
Considering that features are converted to global properties and
global properties are automatically applied to every new instance
of created CPU (at object_new() time), there is no point in
parsing cpu_model string every time a CPU created. So move
parsing outside CPU creation loop and do it only once.

Parsing also should be done before any CPU is created so that
features would affect the first CPU a well.

Backports commit 6aff24c6a61c6fec31e555c7748ba6085b7b2c06 from qemu
2018-03-20 12:27:44 -04:00
Igor Mammedov d5a14f8232
arm: virt: Parse cpu_model only once
Considering that features are converted to global properties and
global properties are automatically applied to every new instance
of created CPU (at object_new() time), there is no point in
parsing cpu_model string every time a CPU created. So move
parsing outside CPU creation loop and do it only once.

Parsing also should be done before any CPU is created so that
features would affect the first CPU a well.

Backports commit 09f71b054a95161950a03fafc9023637929bd404 from qemu
2018-03-20 12:07:03 -04:00
Igor Mammedov 87db6e033b
cpu: Use CPUClass->parse_features() as convertor to global properties
Currently CPUClass->parse_features() is used to parse -cpu
features string and set properties on created CPU instances.

But considering that features specified by -cpu apply to every
created CPU instance, it doesn't make sense to parse the same
features string for every CPU created. It also makes every target
that cares about parsing features string explicitly call
CPUClass->parse_features() parser, which gets in a way if we
consider using generic device_add for CPU hotplug as device_add
has not a clue about CPU specific hooks.

Turns out we can use global properties mechanism to set
properties on every created CPU instance for a given type. That
way it's possible to convert CPU features into a set of global
properties for CPU type specified by -cpu cpu_model and common
Device.device_post_init() will apply them to CPU of given type
automatically regardless whether it's manually created CPU or CPU
created with help of device_add.

Backports commits 62a48a2a5798425997152dea3fc48708f9116c04 and
f313369fdb78f849ecbbd8e5d88f01ddf38786c8 from qemu
2018-03-20 12:00:27 -04:00
Igor Mammedov f86355f82c
cpu: add CPU_RESOLVING_TYPE macro
it will be used for providing to cpu name resolving class for
parsing cpu model for system and user emulation code.

Along with change add target to null-machine tests, so
that when switch to CPU_RESOLVING_TYPE happens,
it would ensure that null-machine usecase still works.

Backports commit 0dacec874fa3b3fd34b0d0670fa257efdcbbebd0 from qemu
2018-03-20 11:28:13 -04:00
Lioncash 14653b00db
qobject: let object_property_get_str() use new API 2018-03-20 11:25:30 -04:00
Peter Xu a6ee6f1a87
qobject: introduce qobject_get_try_str()
A quick way to fetch string from qobject when it's a QString.

Backports commit b26ae1cb8eb0756524e322169138830b9b542311 from qemu
2018-03-20 11:10:03 -04:00
Peter Xu 6446b66dc7
qobject: introduce qstring_get_try_str()
The only difference from qstring_get_str() is that it allows the qstring
to be NULL. If so, NULL is returned.

Backports commit 775932020dd6bd7e9c1acc0d7779677d8b4c094c from qemu
2018-03-20 11:08:40 -04:00
Max Reitz 65b2b73b12
qapi: Make more of qobject_to()
This patch reworks some places which use either qobject_type() checks
plus qobject_to(), where the latter alone is sufficient, or NULL checks
plus qobject_type() checks where we can simply do a qobject_to() != NULL
check.

Backports commit 532fb532847365f61a9c6e1291b6588a43bc1cc4 from qemu
2018-03-20 11:05:44 -04:00
Max Reitz 0c71b44d41
qapi: Remove qobject_to_X() functions
They are no longer needed now.

Backports commit cb51b976babf7ee16dc5eda4f2189d65b8b700a3 from qemu
2018-03-20 10:58:44 -04:00
Max Reitz 275b2ac328
qapi: Replace qobject_to_X(o) by qobject_to(X, o)
This patch was generated using the following Coccinelle script:

@@
expression Obj;
@@
(
- qobject_to_qnum(Obj)
+ qobject_to(QNum, Obj)
|
- qobject_to_qstring(Obj)
+ qobject_to(QString, Obj)
|
- qobject_to_qdict(Obj)
+ qobject_to(QDict, Obj)
|
- qobject_to_qlist(Obj)
+ qobject_to(QList, Obj)
|
- qobject_to_qbool(Obj)
+ qobject_to(QBool, Obj)
)

and a bit of manual fix-up for overly long lines and three places in
tests/check-qjson.c that Coccinelle did not find.

Backports commit 7dc847ebba953db90853d15f140c20eef74d4fb2 from qemu
2018-03-20 10:55:57 -04:00
Max Reitz dbdba16732
qapi: Add qobject_to()
This is a dynamic casting macro that, given a QObject type, returns an
object as that type or NULL if the object is of a different type (or
NULL itself).

The macro uses lower-case letters because:
1. There does not seem to be a hard rule on whether qemu macros have to
be upper-cased,
2. The current situation in qapi/qmp is inconsistent (compare e.g.
QINCREF() vs. qdict_put()),
3. qobject_to() will evaluate its @obj parameter only once, thus it is
generally not important to the caller whether it is a macro or not,
4. I prefer it aesthetically.

The macro parameter order is chosen with typename first for
consistency with other QAPI macros like QAPI_CLONE(), as well as
for legibility (read it as "qobject to" type "applied to" obj).

Backports commit 1a56b1e2ab5e9d6d89386ca953b4afb419e15abe from qemu
2018-03-20 10:45:59 -04:00
Max Reitz 6acf9baa68
compiler: Add QEMU_BUILD_BUG_MSG() macro
_Static_assert() allows us to specify messages, and that may come in
handy. Even without _Static_assert(), encouraging developers to put a
helpful message next to the QEMU_BUILD_BUG_* may make debugging easier
whenever it breaks.

Backports commit 9139b5672360aaa263da1d96cdfdbe16accb6e3b from qemu
2018-03-20 10:43:37 -04:00
Andreas Grapentin 4f6ba5a2dc
use _Static_assert in QEMU_BUILD_BUG_ON
QEMU_BUILD_BUG_ON should use C11's _Static_assert, if the compiler supports it,
to provide more readable messages on failure.

We check for _Static_assert in configure, and set CONFIG_STATIC_ASSERT
accordingly. QEMU_BUILD_BUG_ON invokes _Static_assert if CONFIG_STATIC_ASSERT
is defined, and reverts to the old way otherwise.

That way, systems without C11 conforming compiler will still have the old
messages, as verified by intentionally breaking the configure check.

the following example output was generated by inverting the condition in
QEMU_BUILD_BUG_ON:

without _Static_assert:

> In file included from /qemu/include/qemu/osdep.h:36:0,
> from /qemu/qga/commands.c:13:
> /qemu/qga/commands.c: In function ‘qmp_guest_exec_status’:
> /qemu/include/qemu/compiler.h:89:12: error: negative width in bit-field ‘<anonymous>’
> struct { \
> ^
> /qemu/include/qemu/compiler.h:96:38: note: in expansion of macro QEMU_BUILD_BUG_ON_STRUCT’
> #define QEMU_BUILD_BUG_ON(x) typedef QEMU_BUILD_BUG_ON_STRUCT(x) \
> ^~~~~~~~~~~~~~~~~~~~~~~~
> /qemu/include/qemu/atomic.h:146:5: note: in expansion of macro ‘QEMU_BUILD_BUG_ON’
> QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> ^~~~~~~~~~~~~~~~~
> /qemu/include/qemu/atomic.h:417:5: note: in expansion of macro ‘atomic_load_acquire’
> atomic_load_acquire(ptr)
> ^~~~~~~~~~~~~~~~~~~
> /qemu/qga/commands.c:160:21: note: in expansion of macro ‘atomic_mb_read’
> bool finished = atomic_mb_read(&gei->finished);
> ^~~~~~~~~~~~~~

with _Static_assert:

> In file included from /qemu/include/qemu/osdep.h:36:0,
> from /qemu/qga/commands.c:13:
> /qemu/qga/commands.c: In function ‘qmp_guest_exec_status’:
> /qemu/include/qemu/compiler.h:94:30: error: static assertion failed: "not expecting: sizeof(*&gei->finished) > sizeof(void *)"
> #define QEMU_BUILD_BUG_ON(x) _Static_assert((x), #x)
> ^
> /qemu/include/qemu/atomic.h:146:5: note: in expansion of macro ‘QEMU_BUILD_BUG_ON’
> QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> ^~~~~~~~~~~~~~~~~
> /qemu/include/qemu/atomic.h:417:5: note: in expansion of macro ‘atomic_load_acquire’
> atomic_load_acquire(ptr)
> ^~~~~~~~~~~~~~~~~~~
> /qemu/qga/commands.c:160:21: note: in expansion of macro ‘atomic_mb_read’
> bool finished = atomic_mb_read(&gei->finished);
> ^~~~~~~~~~~~~~

Backports commit 49e00a18708e27c815828d9440d5c9300d19547c from qemu
2018-03-20 10:42:20 -04:00
Marc-André Lureau 910d50be6b
qlit: add qobject_from_qlit()
Instantiate a QObject* from a literal QLitObject.

LitObject only supports int64_t for now. uint64_t and double aren't
implemented.

Backports commit 3cf42b8b3af1bd61e736a9ca0f94806c7931ae56 from qemu
2018-03-20 10:30:41 -04:00
Marc-André Lureau 6b2143ad64
qlit: use QType instead of int
Backports commit 3d96ea44d4dde442094b7d9e5b71ef61b4c4ae39 from qemu
2018-03-20 10:28:12 -04:00
Igor Mammedov c6dd0d3bef
m68k: cleanup cpu type name composition
use new M68K_CPU_TYPE_NAME to compose CPU type names
and get rid of intermediate M68kCPUInfo/register_cpu_type()
which is replaced by static TypeInfo array.

Backports commit f61797bd947cff86b12036917b35ebc38628e4df from qemu
2018-03-20 08:40:05 -04:00
Igor Mammedov 9e175711d6
sparc: cleanup cpu type name composition
introduce SPARC_CPU_TYPE_NAME macro and use it to
construct cpu type names.

Backports commit 1d4bfc5496387124e56df6fd49481e1821403456 from qemu
2018-03-20 08:26:21 -04:00
Eduardo Habkost 074865ff98
cpu: Generify CPU init functions
Backports commits 2994fd96d986578a342f2342501b4ad30f6d0a85,
701e3c78ce45fa630ffc6826c4b9a4218954bc7f, and
d1853231c60d16af78cf4d1608d043614bfbac0b from qemuu
2018-03-20 08:21:51 -04:00
Peter Crosthwaite ce1831bfb4
target-*: Don't redefine cpu_exec()
This function needs to be converted to QOM hook and virtualised for
multi-arch. This rename interferes, as cpu-qom will not have access
to the renaming causing name divergence. This rename doesn't really do
anything anyway so just delete it.

Backports commit 8642c1b81e0418df066a7960a7426d85a923a253 from qemu
2018-03-20 07:02:47 -04:00
Igor Mammedov 15eb359656
numa: move numa_node from CPUState into target specific classes
Move vcpu's associated numa_node field out of generic CPUState
into inherited classes that actually care about cpu<->numa mapping,
i.e: ARMCPU, PowerPCCPU, X86CPU.

Backports relevant parts of commit 15f8b14228b856850df3fa5ba999ad96521f2208 from qemu
2018-03-20 06:46:20 -04:00
Lioncash 6bdfeb35ec
tcg/i386: Perform comparison pass against qemu
Ensures formatting and code are consistent.
2018-03-20 06:29:06 -04:00
Richard Henderson 0dcb2d20ed
tcg: Add choose_vector_size
This unifies 5 copies of checks for supported vector size,
and in the process fixes a missing check in tcg_gen_gvec_2s.

This lead to an assertion failure for 64-bit vector multiply,
which is not available in the AVX instruction set.

Bakports commit adb196cbd5cff26547bc32a208074f03f4c4a627 from qemu
2018-03-17 20:22:31 -04:00
Richard Henderson 2310bd4887
tcg/i386: Support INDEX_op_dup2_vec for -m32
Unknown why -m32 was passing with gcc but not clang; it should have
failed for both. This would be used for tcg_gen_dup_i64_vec, and
visible with the right TB and an aarch64 guest.

Backports commit 7f34ed4bcdfda55f978f51aadca64aa970c9f4b6 from qemu
2018-03-17 20:22:24 -04:00
Richard Henderson e9eee21efd
tcg: Improve tcg_gen_muli_i32/i64
Convert multiplication by power of two to left shift.

Backports commit b2e3ae9452fa55eb036739ec39c33f0782a97504 from qemu
2018-03-17 20:22:10 -04:00
Pavel Dovgalyuk 36d902cd0e
cpu-exec: fix exception_index handling
Function cpu_handle_interrupt calls cc->cpu_exec_interrupt to process
pending hardware interrupts. Under the hood cpu_exec_interrupt uses
cpu->exception_index to pass information to the internal function which
is usually common for exception and interrupt processing.
But this value is not reset after return and may be processed again
by cpu_handle_exception. This does not happen due to overwriting
the exception_index at the end of cpu_handle_interrupt.
But this branch may also overwrite the valid exception_index in some cases.
Therefore this patch:
1. resets exception_index just after the call to cpu_exec_interrupt
2. prevents overwriting the meaningful value of exception_index

Backports commit 5f3bdfd4fa33255542a4b6249913d9ffb11b44f9 from qemu
2018-03-17 19:33:05 -04:00
Paolo Bonzini 7b52aa7987
membarrier: add --enable-membarrier
Actually enable the global memory barriers if supported by the OS.
Because only recent versions of Linux include the support, they
are disabled by default. Note that it also has to be disabled
for QEMU to run under Wine.

Before this patch, rcutorture reports 85 ns/read for my machine,
after the patch it reports 12.5 ns/read. On the other hand updates
go from 50 *micro*seconds to 20 *milli*seconds.

Backports commit a40161cbe9ccbcbab798c3e4d257c4bba99d153a from qemu
2018-03-17 19:30:43 -04:00
Paolo Bonzini 67cb6d16ff
membarrier: introduce qemu/sys_membarrier.h
This new header file provides heavy-weight "global" memory barriers that
enforce memory ordering on each running thread belonging to the current
process. For now, use a dummy implementation that issues memory barriers
on both sides (matching what QEMU has been doing so far).

Backports commit c8d3877e48c4f57381d72eaf8d016bff12ce2d7c from qemu
2018-03-17 19:19:28 -04:00
Paolo Bonzini 37117a74ed
qom: introduce object_class_get_list_sorted
Unify half a dozen copies of very similar code (the only difference being
whether comparisons were case-sensitive) and use it also in Tricore,
which did not do any sorting of CPU model names.

Backports commit 47c66009ab793241e8210b3018c77a9ce9506aa8 from qemu
2018-03-17 19:16:25 -04:00
Daniel P. Berrange 8b20dfcba5
cutils: add qemu_strtoi & qemu_strtoui parsers for int/unsigned int types
There are qemu_strtoNN functions for various sized integers. This adds two
more for plain int & unsigned int types, with suitable range checking.

Backports commit 473a2a331ee382703f7ca0067ba2545350cfa06c from qemu
2018-03-17 19:13:34 -04:00
Chao Peng a64b7f0d3f
i386: Add support to get/set/migrate Intel Processor Trace feature
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.

Backports commit b77146e9a129bcdb60edc23639211679ae846a92 from qemu
2018-03-17 19:11:21 -04:00
Chao Peng da2d5108ee
i386: Add Intel Processor Trace feature support
Expose Intel Processor Trace feature to guest.

To make Intel PT live migration safe and get same CPUID information
with same CPU model on diffrent host. CPUID[14] is constant in this
patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
get on this machine as default value. Intel PT would be disabled
if any machine don't support this minial feature list.

Backports commit e37a5c7fa459558b5020588994707fe3fdd6616e from qemu
2018-03-17 19:10:30 -04:00
Wanpeng Li f0701e6dd5
target-i386: add KVM_HINTS_DEDICATED performance hint
Add KVM_HINTS_DEDICATED performance hint, guest checks this feature bit
to determine if they run on dedicated vCPUs, allowing optimizations such
as usage of qspinlocks.

Backports commit be7773268d98176489483a315d3e2323cb0615b9 from qemu
2018-03-17 19:07:19 -04:00
Liran Alon 9fbdd8d885
KVM: x86: Add support for save/load MSR_SMI_COUNT
This MSR returns the number of #SMIs that occurred on
CPU since boot.

KVM commit 52797bf9a875 ("KVM: x86: Add emulation of MSR_SMI_COUNT")
introduced support for emulating this MSR.

This commit adds support for QEMU to save/load this
MSR for migration purposes.

Backports relevant parts of commit e13713db5b609d9a83c9cfc8ba389d4215d4ba29 from qemu
2018-03-17 19:02:31 -04:00
Brijesh Singh 624391bdc8
cpu/i386: populate CPUID 0x8000_001F when SEV is active
When SEV is enabled, CPUID 0x8000_001F should provide additional
information regarding the feature (such as which page table bit is used
to mark the pages as encrypted etc).

The details for memory encryption CPUID is available in AMD APM
(https://support.amd.com/TechDocs/24594.pdf) Section E.4.17

Backports relevant parts of commit 6cb8f2a663a47c6e0da17fc4fb9e06abfda2bd48 from qemu
2018-03-17 19:00:59 -04:00
Laurent Vivier 5ec082d17c
target/m68k: implement fcosh
Using a local m68k floatx80_cosh()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 02f9124ebe26c36f0f7ed58085bd963e4372b2cd from qemu
2018-03-17 18:58:57 -04:00
Laurent Vivier 7569530893
target/m68k: implement fsinh
Using a local m68k floatx80_sinh()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit eee6b892a6063c2807ecf33a2f62a8d7cca7652c from qemu
2018-03-17 18:57:16 -04:00
Laurent Vivier a2a662a901
target/m68k: implement ftanh
Using local m68k floatx80_tanh() and floatx80_etoxm1()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 9937b02965c2a7dbc4b21d98e29b082bab095aa5 from qemu
2018-03-17 18:55:33 -04:00
Laurent Vivier e031b14e4a
target/m68k: implement fatanh
Using a local m68k floatx80_atanh()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit e3655afa137b2e0999537eef273a2845ba21d68c from qemu
2018-03-17 18:54:24 -04:00
Laurent Vivier c900ad13f9
target/m68k: implement facos
Using a local m68k floatx80_acos()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit c84813b807fc82c68ff6d72387f95b15ad283bf6 from qemu
2018-03-17 18:52:27 -04:00
Laurent Vivier 542a863020
target/m68k: implement fasin
Using a local m68k floatx80_asin()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit bc20b34e03b51725d7f008551b5f56f1da07ab6a from qemu
2018-03-17 18:50:30 -04:00
Laurent Vivier 80a2ebf67b
target/m68k: implement fatan
Using a local m68k floatx80_atan()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 8c992abc892c90caf1d4dd5b4482cda052a280ba from qemu
2018-03-17 18:48:32 -04:00
Laurent Vivier 5630647279
target/m68k: implement fsincos
using floatx80_sin() and floatx80_cos()

Backports commit 47446c9ce34b6685ffe20e829ff6c9aaefd3af0a from qemu
2018-03-17 18:41:30 -04:00
Laurent Vivier 4177dd3ce8
target/m68k: implement fcos
Using a local m68k floatx80_cos()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 68d0ed37866de2c5cafc4e2589e263961b2e8cd6 from qemu
2018-03-17 18:39:05 -04:00
Laurent Vivier acc9bd1d21
target/m68k: implement fsin
Using a local m68k floatx80_sin()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 5add1ac42faffd3d3639101fa778dced693a65a3 from qemu
2018-03-17 18:37:01 -04:00
Laurent Vivier caf3cb0571
target/m68k: implement ftan
Using a local m68k floatx80_tan()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 273401809c8a8330e5430f2c958467efa7079b2c from qemu
2018-03-17 18:35:01 -04:00
Lioncash 103af93402
translate-all: Prevent null-pointer dereference possibility in tb_clean_internal() 2018-03-17 18:31:39 -04:00
Lioncash 1fe99928c8
target/m68k: Correct M68K_CPU macro parameters in m68k_cpu_handle_mmu_fault in helper.c 2018-03-17 18:31:06 -04:00
Lioncash c169f3dc5d
target/i386: Correct X86_CPU macro parameters in x86_cpu_handle_mmu_fault() in helper.c 2018-03-17 18:30:46 -04:00
Lioncash acb7231650
target/m68k: Correct duplicate conditions in gen_cc_cond 2018-03-17 18:30:33 -04:00
Richard Henderson 31e93018f3
tcg: Allow 6 arguments to TCG helpers
We already handle this in the backends, and the lifetime datum
for the TCGOp is already large enough.

Backports commit 1df3caa946e08b387511dfba3a37d78910e51796 from qemu
2018-03-17 18:29:04 -04:00
Philippe Mathieu-Daudé 4eeb4f7faf
accel/tcg: move atomic_template.h to accel/tcg/ 2018-03-13 12:28:50 -04:00
Thomas Huth 975924bb2e
accel/tcg: move softmmu_template.h to accel/tcg/
The header is only used by accel/tcg/cputlb.c so we can
move it to the accel/tcg/ folder, too.

Backports commit da1849c1eba50aa372f87c7945d7b230eb2b2fb2 from qemu
2018-03-13 12:27:04 -04:00
Lioncash 035f1afa7d
tcg: move tcg backend files into accel/tcg/
move tcg-runtime.c, translate-all.(ch) and translate-common.c into
accel/tcg/ subdirectory and updated related trace-events file.

Backports commit 244f144134d0dd182f1af8654e7f9a79fe770368 and applies
relevant changes made in db432672dc50ed86dda17ac821b7eb07411a90af and
d9bb58e51068dfc48746c6af0179926c8dc05bce from qemu
2018-03-13 11:48:15 -04:00
Lioncash 99dbbf1571
tcg/optimize: Perform comparison pass with qemu
Keeps formatting and code synced
2018-03-12 18:06:29 -04:00
Lioncash 21b0afe218
tcg: Perform comparison pass with qemu
Makes formatting and code consistent with qemu
2018-03-12 18:03:06 -04:00
Lioncash 95d50a02a1
target/mips/translate: Perform comparison pass with qemu
Keeps code and formatting in sync
2018-03-12 17:52:56 -04:00
Lioncash 7db1bff993
target/mips/op_helper: Perform comparison pass with qemu
Keeps code and formatting in sync
2018-03-12 15:25:08 -04:00
Lioncash 48429b2bcb
target/mips/msa_helper: Perform comparison pass with qemu
Keeps code and formatting in sync
2018-03-12 15:15:42 -04:00
Lioncash 4e8a1f8d6b
target/mips/internal: Perform comparison pass with qemu
Keeps code and formatting in sync with qemu
2018-03-12 15:13:17 -04:00
Lioncash 05089ecb12
target/mips/helper: Perform comparison pass with qemu
Keeps code and formatting in sync with qemu
2018-03-12 15:11:52 -04:00
Lioncash 56675f5215
cpu-exec: Resolve potential compilation errors
We need to pass 'uc' to CPU_GET_CLASS
2018-03-12 14:59:21 -04:00
Lioncash e9d9ed5eaa
target/i386/bpt_helper: Perform comparison pass with qemu
Keep formatting and code in sync where applicable
2018-03-12 13:28:50 -04:00
Lioncash fc7eaf7f77
target/i386/svm_helper: Perform comparison pass with qemu
Keep code and formatting in sync where applicable
2018-03-12 13:27:03 -04:00
Lioncash 27c283bb3c
target/i386/smm_helper: Perform comparison pass with qemu
Ensure code and formatting stay in sync where relevant
2018-03-12 13:25:37 -04:00
Lioncash 73426a7e79
target/i386/seg_helper: Perform comparison pass against qemu
Ensure formatting and code stay in sync where relevant
2018-03-12 13:24:36 -04:00
Lioncash a1910954cd
target/i386/mem_helper: Perform comparison pass against qemu
Ensure formatting and relevant code are in order
2018-03-12 13:19:05 -04:00
Lioncash 995ae229a3
target/i386/excp_helper: remove unnecessary comment 2018-03-12 13:16:53 -04:00
Lioncash c1e72be68d
target/i386/fpu_helper: Perform comparison pass against qemu 2018-03-12 13:15:51 -04:00
Lioncash 0d0dd2ba98
target/i386/translate: Perform comparison pass against qemu
Ensure code and formatting match qemu where applicable
2018-03-12 13:12:01 -04:00
Lioncash 83b35aa797
target/sparc/win_helper: Perform comparison pass against qemu
Ensure code and formatting are consistent with qemu
2018-03-12 12:46:59 -04:00
Lioncash 0215431990
target/sparc/mmu_helper: Perform comparison pass against qemu
Ensure code and formatting match qemu
2018-03-12 12:45:18 -04:00
Lioncash 83c0769d90
target/sparc/ldst_helper: Perform comparison pass against qemu
Ensure code and formatting is consistent with qemu
2018-03-12 12:43:14 -04:00
Lioncash a228660860
target/sparc/fop_helper: Perform comparison pass against qemu
Ensure formatting and code is consistent from the backporting
2018-03-12 12:38:21 -04:00
Lioncash 2114d28f7e
target/sparc/cc_helper: Perform a comparison pass against qemu 2018-03-12 12:36:51 -04:00
Lioncash bcc8bc5c18
target/sparc/translate: Perform comparison pass againt main qemu repo
Ensure that formatting and relevant code is organized like qemu
2018-03-12 12:34:49 -04:00
Lioncash b92dd8d299
target/m68k/op_helper: Adjust formatting to be in sync with qemu 2018-03-12 12:26:53 -04:00
Lioncash 6e9ecb876e
target/m68k/translate: Perform pass over code relative to qemu
Catches a few things that got lost in the backporting process.
2018-03-12 12:22:57 -04:00
Lioncash 750d56421c
translate/arm/vec_helper: Align to qemu formatting 2018-03-12 11:59:14 -04:00
Lioncash bab31a2510
target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style 2018-03-12 11:57:24 -04:00
Lioncash 0751366e5c
target/arm/op_helper: Correct bad merge 2018-03-12 11:42:43 -04:00
Lioncash 9a0632bfcf
target/arm/helper64: Correct bad merge 2018-03-12 11:37:27 -04:00
Lioncash c93c3bd4b3
target/arm/helper: Correct bad merge 2018-03-12 11:33:45 -04:00
Lioncash 14c1fcd5bf
target/arm/translate: Correct bad merge 2018-03-12 11:17:37 -04:00
Lioncash 0dd13de42f
target/arm/translate-a64: Correct bad merge 2018-03-12 11:17:33 -04:00
Peter Maydell fabd6c7ae8
target/arm: Make 'any' CPU just an alias for 'max'
Now we have a working '-cpu max', the linux-user-only
'any' CPU is pretty much the same thing, so implement it
that way.

For the moment we don't add any of the extra feature bits
to the system-emulation "max", because we don't set the
ID register bits we would need to to advertise those
features as present.

Backports commit a0032cc5427d0d396aa0a9383ad9980533448ea4 from qemu
2018-03-12 10:11:49 -04:00
Peter Maydell 7388fff079
target/arm: Add "-cpu max" support
Add support for "-cpu max" for ARM guests. This CPU type behaves
like "-cpu host" when KVM is enabled, and like a system CPU with
the maximum possible feature set otherwise. (Note that this means
it won't be migratable across versions, as we will likely add
features to it in future.)

Backports commit bab52d4bba3f22921a690a887b4bd0342f2754cd from qemu
2018-03-12 10:11:49 -04:00
Alistair Francis 44d8c38138
target/arm: Add a core count property
The cortex A53 TRM specifies that bits 24 and 25 of the L2CTLR register
specify the number of cores in the processor, not the total number of
cores in the system. To report this correctly on machines with multiple
CPU clusters (ARM's big.LITTLE or Xilinx's ZynqMP) we need to allow
the machine to overwrite this value. To do this let's add an optional
property.

Backports commit f9a697112ee64180354f98309a5d6b691cc8699d from qemu
2018-03-12 10:11:48 -04:00
Kevin Wolf 025e354370
qdict: Introduce qdict_rename_keys()
A few block drivers will need to rename .bdrv_create options for their
QAPIfication, so let's have a helper function for that.

Backports commit bcebf102ccc3c6db327f341adc379fdf0673ca6b from qemu
2018-03-12 10:11:48 -04:00
Laurent Vivier 418f96df9b
target/m68k: implement ftentox
Using a local m68k floatx80_tentox()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 6c25be6e30bda0e470f8f0b6b93d53a6efe469e8 from qemu
2018-03-12 10:11:48 -04:00
Laurent Vivier 61fa8cf539
target/m68k: implement ftwotox
Using a local m68k floatx80_twotox()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 068f161536d9a28a5bc482f3de9c387b2fe5908d from qemu
2018-03-12 10:11:48 -04:00
Laurent Vivier 5d508f45b6
target/m68k: implement fetox
Using a local m68k floatx80_etox()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 40ad087330bee5394c9e78c97f909f580be69b58 from qemu
2018-03-12 10:11:47 -04:00
Laurent Vivier 2b793fce0f
target/m68k: implement flog2
Using a local m68k floatx80_log2()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 67b453ed73fe65949c24e6ca2b43f6816a89a301 from qemu
2018-03-12 10:11:47 -04:00
Laurent Vivier a052fcb40b
target/m68k: implement flog10
Using a local m68k floatx80_log10()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 248efb66fb88bc17c04a0d0f09a3539a43c80769 from qemu
2018-03-12 10:11:47 -04:00
Laurent Vivier 9852c8c94a
target/m68k: implement flogn
Using a local m68k floatx80_logn()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 50067bd16fead5d78a283130efbf3e3b026de450 from qemu
2018-03-12 10:11:47 -04:00
Laurent Vivier 442aa7a87a
target/m68k: implement flognp1
Using a local m68k floatx80_lognp1()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 4b5c65b8f02a057bc1b77839b5012544f96fec80 from qemu
2018-03-12 10:11:47 -04:00
Laurent Vivier 5bc9cdb681
target/m68k: define floatx80_move()
This functions is needed by upcoming m68k softfloat functions.

Source code copied for WinUAE (tag 3500)
(The WinUAE file has been copied from QEMU and has
the QEMU licensing notice)

Backports commit 9a069775a8087cbd6fa8c479b69be8d37bd90351 from qemu
2018-03-12 10:11:46 -04:00
Lioncash a81439c7ca
exec: Drop unnecessary code for unicorn
The dirty memory code isn't strictly necessary
2018-03-12 10:11:46 -04:00
Lioncash b28c64ed34
tcg/i386: Amend bad merge 2018-03-12 10:11:03 -04:00
Richard Henderson a16ee979fc
tcg/i386: Always use TZCNT when available
I think this is cleaner than sometimes using BSF.

Backports commit 39f099ec9d6d420b6fe6f7f4f8ed80ae29c65ff2 from qemu
2018-03-12 05:11:42 -04:00
Lioncash 8e161bb723
target/arm: Use the any cpu model instead of cortex-a57
The Cortex-A57 doesn't allow use of v8.1+ architecture instructions
2018-03-12 03:42:57 -04:00
Alexey Kardashevskiy b90333a531
memory: Share special empty FlatView
This shares an cached empty FlatView among address spaces. The empty
FV is used every time when a root MR renders into a FV without memory
sections which happens when MR or its children are not enabled or
zero-sized. The empty_view is not NULL to keep the rest of memory
API intact; it also has a dispatch tree for the same reason.

On POWER8 with 255 CPUs, 255 virtio-net, 40 PCI bridges guest this halves
the amount of FlatView's in use (557 -> 260) and dispatch tables
(~800000 -> ~370000). In an unrelated experiment with 112 non-virtio
devices on x86 ("-M pc"), only 4 FlatViews are alive, and about ~2000
are created at startup.

Backports commit 092aa2fc65b7a35121616aad8f39d47b8f921618 from qemu
2018-03-11 22:34:28 -04:00
Paolo Bonzini 20b1bd767f
memory: seek FlatView sharing candidates among children subregions
A container can be used instead of an alias to allow switching between
multiple subregions. In this case we cannot directly share the
subregions (since they only belong to a single parent), but if the
subregions are aliases we can in turn walk those.

This is not enough to remove all source of quadratic FlatView creation,
but it enables sharing of the PCI bus master FlatViews (and their
AddressSpaceDispatch structures) across all PCI devices. For 112
virtio-net-pci devices, boot time is reduced from 25 to 10 seconds and
memory consumption from 1.4 to 1 G.

Backports commit e673ba9af9bf8fd8e0f44025ac738b8285b3ed27 from qemu
2018-03-11 22:19:55 -04:00
Alexey Kardashevskiy 7eab335b2e
memory: Create FlatView directly
This avoids usual memory_region_transaction_commit() which rebuilds
all FVs.

On POWER8 with 255 CPUs, 255 virtio-net, 40 PCI bridges guest this brings
down the boot time from 25s to 20s and reduces the amount of temporary FVs
allocated during machine constructon (~800000 -> ~640000) and amount of
temporary dispatch trees (~370000 -> ~300000), the total memory footprint
goes down (18G -> 17G).

Backports commit 202fc01b05572ecb258fdf4c5bd56cf6de8140c7 from qemu
2018-03-11 22:17:48 -04:00
Alexey Kardashevskiy 1fd8b64072
memory: Get rid of address_space_init_shareable
Since FlatViews are shared now and ASes not, this gets rid of
address_space_init_shareable().

This should cause no behavioural change.

Backports commit b516572f31c0ea0937cd9d11d9bd72dd83809886 from qemu
2018-03-11 22:12:38 -04:00
Alexey Kardashevskiy 34709f52ee
memory: Do not allocate FlatView in address_space_init
This creates a new AS object without any FlatView as
memory_region_transaction_commit() may want to reuse the empty FV.

Backports commit 67ace39b253ed5ae465275bc870f7e495547658b from qemu
2018-03-11 22:07:36 -04:00
Alexey Kardashevskiy f2c72dc278
memory: Share FlatView's and dispatch trees between address spaces
This allows sharing flat views between address spaces (AS) when
the same root memory region is used when creating a new address space.
This is done by walking through all ASes and caching one FlatView per
a physical root MR (i.e. not aliased).

This removes search for duplicates from address_space_init_shareable() as
FlatViews are shared elsewhere and keeping as::ref_count correct seems
an unnecessary and useless complication.

This should cause no change and memory use or boot time yet.

Backports commit 967dc9b1194a9281124b2e1ce67b6c3359a2138f from qemu
2018-03-11 22:05:44 -04:00
Alexey Kardashevskiy 0d9fe8e20c
memory: Alloc dispatch tree where topology is generared
This is to make next patches simpler.

Backports commit 9bf561e36cf8fed9565011a19ba9ea0100e1811e from qemu
2018-03-11 21:43:23 -04:00
Alexey Kardashevskiy 037d039a4d
memory: Store physical root MR in FlatView
Address spaces get to keep a root MR (alias or not) but FlatView stores
the actual MR as this is going to be used later on to decide whether to
share a particular FlatView or not.

Backports commit 89c177bbdd6cf8e50b3fd4831697d50e195d6432 from qemu
2018-03-11 21:39:37 -04:00
Alexey Kardashevskiy d9bc1bcc8c
memory: Rename mem_begin/mem_commit/mem_add helpers
This renames some helpers to reflect better what they do.

This should cause no behavioural change.

Backports commit 8629d3fcb77e9775e44d9051bad0fb5187925eae from qemu
2018-03-11 21:36:50 -04:00
Alexey Kardashevskiy 489abbbd8b
memory: Cleanup after switching to FlatView
We store AddressSpaceDispatch* in FlatView anyway so there is no need
to carry it from mem_add() to register_subpage/register_multipage.

This should cause no behavioural change.

Backports commit 9950322a593ff900a860fb52938159461798a831 from qemu
2018-03-11 21:27:51 -04:00
Alexey Kardashevskiy aa2b76b4e8
memory: Switch memory from using AddressSpace to FlatView
FlatView's will be shared between AddressSpace's and subpage_t
and MemoryRegionSection cannot store AS anymore, hence this change.

In particular, for:

typedef struct subpage_t {
MemoryRegion iomem;
- AddressSpace *as;
+ FlatView *fv;
hwaddr base;
uint16_t sub_section[];
} subpage_t;

struct MemoryRegionSection {
MemoryRegion *mr;
- AddressSpace *address_space;
+ FlatView *fv;
hwaddr offset_within_region;
Int128 size;
hwaddr offset_within_address_space;
bool readonly;
};

This should cause no behavioural change.

Backports commit 166206845f7fd75e720e6feea0bb01957c8da07f from qemu
2018-03-11 21:21:37 -04:00
Alexey Kardashevskiy 06b53d8e40
memory: Remove AddressSpace pointer from AddressSpaceDispatch
AS in ASD is only used to pass AS from mem_begin() to register_subpage()
to store it in MemoryRegionSection, we can do this directly now.

This should cause no behavioural change.

Backports commit c7752523787dc148f5ee976162e80ab594c386a1 from qemu
2018-03-11 20:45:43 -04:00
Lioncash 1591f208c0
memory: Move AddressSpaceDispatch from AddressSpace to FlatView
As we are going to share FlatView's between AddressSpace's,
and AddressSpaceDispatch is a structure to perform quick lookup
in FlatView, this moves ASD to FlatView.

After previosly open coded ASD rendering, we can also remove
as->next_dispatch as the new FlatView pointer is stored
on a stack and set to an AS atomically.

flatview_destroy() is executed under RCU instead of
address_space_dispatch_free() now.

This makes mem_begin/mem_commit to work with ASD and mem_add with FV
as later on mem_add will be taking FV as an argument anyway.

This should cause no behavioural change.

Backports commit 66a6df1dc6d5b28cc3e65db0d71683fbdddc6b62 from qemu
2018-03-11 20:40:24 -04:00
Lioncash cc8fd90124
unicorn_common: Eliminate memory leaks 2018-03-11 20:20:29 -04:00
Marc-André Lureau aee9f7327f
machine: use class base init generated name
machine_class_base_init() member name is allocated by
machine_class_base_init(), but not freed by
machine_class_finalize().  Simply freeing there doesn't work,
because DEFINE_PC_MACHINE() overwrites it with a literal string.

Fix DEFINE_PC_MACHINE() not to overwrite it, and add the missing
free to machine_class_finalize().

Backports commit 8ea753718b2d1a42e9ce7b8db9f5e4e1f330e827 from qemu
2018-03-11 16:54:40 -04:00
Lioncash 8648b1df4f
include/elf: Update elf.h to commit f71a8eaffba3271cf7cdad95572f6996f7523a5b 2018-03-11 15:34:35 -04:00
Eduardo Habkost 7c7bb4c6d1
machine: Eliminate QEMUMachine and qemu_register_machine()
The struct is not used anymore and can be eliminated.

Backports commit 3b53e45f43825caaaf4fad6a5b85ce6a9949ff02 from qemu
2018-03-11 15:22:25 -04:00
Andreas Färber 048aaf05ca
Revert use of DEFINE_MACHINE() for registrations of multiple machines
The script used for converting from QEMUMachine had used one
DEFINE_MACHINE() per machine registered. In cases where multiple
machines are registered from one source file, avoid the excessive
generation of module init functions by reverting this unrolling.

Backports commit 8a661aea0e7f6e776c6ebc9abe339a85b34fea1d from qemu
2018-03-11 15:17:17 -04:00
Eduardo Habkost a7f59d7771
Use DEFINE_MACHINE() to register all machines
Convert all machines to use DEFINE_MACHINE() instead of QEMUMachine
automatically using a script.

Backports commit e264d29de28c5b0be3d063307ce9fb613b427cc3 from qemu
2018-03-11 15:12:46 -04:00
Eduardo Habkost 426b961644
machine: DEFINE_MACHINE() macro
The macro will allow easy registration of a TYPE_MACHINE subclass, using
only the machine name and a MachineClass initialization function as
parameter.

Backports commit ed0b6de343448d1014b53bcf541041373322fa1c from qemu
2018-03-11 14:42:12 -04:00
Eduardo Habkost 46e1c5482b
machine: Set MachineClass::name automatically
Now all TYPE_MACHINE subclasses use MACHINE_TYPE_NAME to generate the
class name. So instead of requiring each subclass to set
MachineClass::name manually, we can now set it automatically at the
TYPE_MACHINE class_base_init() function.

Backports commit 98cec76a7076c4a38e16f1a9de170a7942b3be54 from qemu
2018-03-11 14:38:58 -04:00
Eduardo Habkost 0261df973b
machine: Ensure all TYPE_MACHINE subclasses have the right suffix
Now that all non-abstract TYPE_MACHINE subclasses have the -machine
suffix, add an assert to ensure this will be always true.

Backports commit dcb3d601115eed77aef543fe3a920adc17544e06 from qemu
2018-03-11 14:30:38 -04:00
Eduardo Habkost 1b2aee0a86
arm: Rename virt machine class to use MACHINE_TYPE_NAME
Machine class names should use the "-machine" suffix to allow
class-name-based machine class lookup to work. Rename the arm virt
machine class using the MACHINE_TYPE_NAME macro.

Backports commit 64d3459c8586c8821970cbc99450340278507cfe from qemu
2018-03-11 14:20:58 -04:00
Greg Bellows 655b780f48
target-arm: Add virt machine secure property
Add "secure" virt machine specific property to allow override of the
default secure state configuration. By default, when using the QEMU
-kernel command line argument, virt machines boot into NS/SVC. When using
the QEMU -bios command line argument, virt machines boot into S/SVC.

The secure state can be changed from the default specifying the secure
state as a machine property. For example, the below command line would disable
security extensions on a -kernel Linux boot:

aarch64-softmmu/qemu-system-aarch64
-machine type=virt,secure=off
-kernel ...

Backports commit 083a58906cb32731dd98a93fcf451ec7718c0924 from qemu
2018-03-11 14:11:17 -04:00
Greg Bellows 125bd964d9
target-arm: Add virt class and machine types
Switch virt qemu machine support to use the newer object type, class, and
instance model. Added virt TypeInfo with static registration along with virt
specific class and machine structs. Also added virt class initialization
method.

Backports commit c29196904b2bad015edc553a5693c5c9e6f8177a from qemu
2018-03-11 14:03:34 -04:00
Eduardo Habkost df4cfe6804
machine: MACHINE_TYPE_NAME macro
The macro will be useful to ensure the machine class names follow the
right format to make machine class lookup by class name work correctly.

Backports commit c84a8f01b2a5d8bf98c447796d4a747333a5b1fd from qemu
2018-03-11 13:44:26 -04:00
Eduardo Habkost ba09afc8b5
pc: Generate init functions with a macro
All pc-i440fx and pc-q35 init functions simply call the corresponding
compat function and then call the main init function. Use a macro to
generate that code.

Backports commit 99fbeafee8b568e796863980365080abdb8d675e from qemu
2018-03-11 13:42:19 -04:00
Eduardo Habkost 6a287ba88e
piix: Eliminate pc_init_pci()
Backports commit 211b5b1d0a31f2f7593d6858a0b10487fb7b7fac from qemu
2018-03-11 13:38:06 -04:00
Eduardo Habkost 940d2371ea
machine: Remove unused fields from QEMUMachine
This removes the following fields from QEMUMachine: family, alias,
reset, hot_add_cpu, units_per_default_bus, no_serial, no_parallel,
use_virtcon, use_sclp, no_floppy, no_cdrom, default_display,
compat_props, and hw_version.

The only users of those fields were already converted to use QOM and
MachineClass directly, so they are not needed anymore.

Backports commit d48f4fa69eb3efb03a2efe2e4606a97a17cf222f from qemu
2018-03-09 14:26:23 -05:00
Eduardo Habkost 12acb995fa
pc: Don't use QEMUMachine anymore
Now that we have a DEFINE_PC_MACHINE helper macro that just requires an
initialization function, it is trivial to convert them to register a QOM
machine class directly, instead of using QEMUMachine.

Backports commit 865906f7fdadd2732441ab158787f81f6a212bfe from qemu
2018-03-09 14:22:43 -05:00
Eduardo Habkost b65a3ece3b
machine: Remove unused fields from QEMUMachine
This removes the following fields from QEMUMachine: family, alias,
reset, hot_add_cpu, units_per_default_bus, no_serial, no_parallel,
use_virtcon, use_sclp, no_floppy, no_cdrom, default_display,
compat_props, and hw_version.

The only users of those fields were already converted to use QOM and
MachineClass directly, so they are not needed anymore.

Backports commit d48f4fa69eb3efb03a2efe2e4606a97a17cf222f from qemu
2018-03-09 13:41:30 -05:00
Marc-André Lureau 9ec040b74d
bus: simplify name handling
Simplify a bit the code by using g_strdup_printf() and store it in a
non-const value so casting is no longer needed, and ownership is
clearer.

Backports commit f73480c36f49562556b80bb5bf8acc45e20dcca1 from qemu
2018-03-09 13:02:15 -05:00
Thomas Huth af3cd62c4b
Introduce DEVICE_CATEGORY_CPU for CPU devices
Now that CPUs show up in the help text of "-device ?",
we should group them into an appropriate category.

Backports commit ba31cc7226ebcee639f18faa90c1542bd364fba3 from qemu
2018-03-09 13:00:32 -05:00
Peter Maydell 714781d9e0
configure: Never use 'uname' to identify target OS
For a very long time we have used 'uname -s' as our fallback if
we don't identify the target OS using a compiler #define. This
obviously doesn't work for cross-compilation, and we've had
a comment suggesting we fix this in configure for a long time.
Since we now have an exhaustive list of which OSes we can run
on (thanks to commit 898be3e0415 making an unrecognized OS
be a fatal error), we know which ones we're missing.

Add check_define tests for the remaining OSes we support. The
defines checked are based on ones we already use in the codebase for
identifying the host OS (with the exception of GNU/kFreeBSD).
We can now set bogus_os immediately rather than doing it later.

We leave the comment about uname being bad untouched, since
there is still a use of it for the fallback for unrecognized
host CPU type.

Backports commit 951fedfceeda1b09ac8aa1f5263288b65e13caca from qemu
2018-03-09 12:37:21 -05:00
Peter Maydell 9601f82746
configure: Diagnose broken linkers directly
Currently if the user's compiler works for creating .o files but
their linker is broken such that compiling an executable from a
C file does not work, we will report a misleading error message
about the compiler not supporting __thread (since that happens
to be the first test we run which requires a working linker).
Explicitly check that compile_prog works as well as compile_object,
so that people whose toolchain setup is broken get a more helpful
error message.

Backports commit 0ef74c7496fd3c526b2259f86326eca4b3a03b78 from qemu
2018-03-09 12:26:21 -05:00
Peter Maydell 91de4878f7
configure: Don't claim 'unsupported host OS' when better message available
The change in commit 898be3e0415c6d which made completely
unrecognized OSes cause an error_exit "Unsupported host OS"
has some unfortunate unintended effects:
* if you run 'configure --help' on an unsupported host OS
(eg if intending to use it as a build machine for a
cross compile to a supported host) then the message
is printed instead of --help
* if the C compiler doesn't work or is missing (eg if
you passed an incorrect --cross-prefix by mistake)
the message is printed instead of the more useful
'compiler does not exist or does not work' message

Fix this by postponing the error_exit in this situation
until later, when we have already identified the more
useful cases for this.

The long term fix for this would be to move handling
of --help much further up in the configure script,
and make its output not dependent on checks that configure
runs. However for 2.9 this would be too invasive.

Backports commit fb59dabd4fa7e6586824ac3012073b943fc8dc79 from qemu
2018-03-09 12:25:14 -05:00
Peter Maydell a3ae5a783f
configure: Warn about deprecated hosts
We plan to drop support in a future QEMU release for host OSes
and host architectures for which we have no test machine where
we can build and run tests. For the 2.9 release, make configure
print a warning if it is run on such a host, so that the user
has some warning of the plans and can volunteer to help us
maintain the port if they need it to continue to function.

This commit flags up as deprecated the CPU architectures:
* ia64
* sparc
* anything which we don't have a TCG port for
(and which was presumably using TCI)
and the OSes:
* GNU/kFreeBSD
* DragonFly BSD
* NetBSD
* OpenBSD
* Solaris
* AIX
* Haiku

It also makes entirely unrecognized host OS strings be
rejected rather than treated as if they were Linux (which
likely never worked).

Backports commit 898be3e0415c6d614395c087ef1e91210797cda7 from qemu
2018-03-09 12:21:12 -05:00
Peter Maydell 4149e877c4
configure: Drop ancient Solaris 9 and earlier support
Solaris 9 was released in 2002, its successor Solaris 10 was
released in 2005, and Solaris 9 was end-of-lifed in 2014.
Nobody has stepped forward to express interest in supporting
Solaris of any flavour, so removing support for the ancient
versions seems uncontroversial.

In particular, this allows us to remove a use of 'uname'
in configure that won't work if you're cross-compiling.

Backports commit 91939262ffcd3c85ea6a4793d3029326eea1d649 from qemu
2018-03-09 12:14:21 -05:00
Richard Henderson 7e327aaf84
util: Introduce include/qemu/cpuid.h
Clang 3.9 passes the CONFIG_AVX2_OPT configure test. However, the
supplied <cpuid.h> does not contain the bit_AVX2 define that we use
when detecting whether the routine can be enabled.

Introduce a qemu-specific header that uses the compiler's definition
of __cpuid et al, but supplies any missing bit_* definitions needed.
This avoids introducing any extra ifdefs to util/bufferiszero.c, and
allows quite a few to be removed from tcg/i386/tcg-target.inc.c.

Backports commit 5dd8990841a9e331d9d4838a116291698208cbb6 from qemu
2018-03-09 12:12:00 -05:00
Peter Maydell 6d0e83d218
Drop remaining bits of ia64 host support
We dropped support for ia64 host CPUs in the 2.11 release (removing
the TCG backend for it, and advertising the support as being
completely removed in the changelog).  However there are a few bits
and pieces of code still floating about.  Remove those, too.

We can drop the check in configure for "ia64 or hppa host?"
entirely, because we don't support hppa hosts either any more.

Backports commit b1cef6d02f84bd842fb94a6109ad4e2ad873e8e5 from qemu
2018-03-09 11:54:57 -05:00
Marc-André Lureau 234f2ca184
build-sys: fix -fsanitize=address check
Since 218bb57dd79d6843e0592c30a82ea8c1fddc74a5, the -fsanitize=address
check fails with:
config-temp/qemu-conf.c:3:20: error: integer overflow in expression [-Werror=overflow]
return INT32_MIN / -1;

Interestingly, UBSAN check doesn't produce a compile time warning.
Use a test that doesn't have compile time warnings, and make it
specific to UBSAN check.

Backports commit b9f44da2f2cdc1a1a1be5aed0c46bd7fcc69cf4a from qemu
2018-03-09 11:52:00 -05:00
John Snow 0aa640a303
configure: factor out supported flag check
Factor out the function that checks if a compiler
flag is supported or not.

Backports commit 93b25869228a3c0c632a6aa66624cc4e549ba14a from qemu
2018-03-09 11:49:37 -05:00
Stef O'Rear d25e1a6216
softfloat: fix crash on int conversion of SNaN
Backports commit cffad426f520d39c19db64485d8a429fc95b8aca from qemu
2018-03-09 11:40:17 -05:00
Markus Armbruster 4b61859c3c
qapi: Don't create useless directory qapi-generated
We used to generate first test and later QGA QAPI code into
qapi-generated/. Commit b93b63f574 moved the test code to tests/.
Commit 54c2e50205 moved the QGA code to qga/qapi-generated/. The
directory has been unused since.

Backports commit 418b1d0ae3a2cc992659f626a2a3f11944e0b259 from qemu
2018-03-09 11:36:49 -05:00
Markus Armbruster 3277400723
qapi: Move qapi-schema.json to qapi/, rename generated files
Move qapi-schema.json to qapi/, so it's next to its modules, and all
files get generated to qapi/, not just the ones generated for modules.

Consistently name the generated files qapi-MODULE.EXT:
qmp-commands.[ch] become qapi-commands.[ch], qapi-event.[ch] become
qapi-events.[ch], and qmp-introspect.[ch] become qapi-introspect.[ch].
This gets rid of the temporary hacks in scripts/qapi/commands.py,
scripts/qapi/events.py, and scripts/qapi/common.py.

Backports commit eb815e248f50cde9ab86eddd57eca5019b71ca78 from qemu
2018-03-09 11:35:11 -05:00
Markus Armbruster 311d659acf
qapi: Empty out qapi-schema.json
The previous commit improved compile time by including less of the
generated QAPI headers. This is impossible for stuff defined directly
in qapi-schema.json, because that ends up in headers that that pull in
everything.

Move everything but include directives from qapi-schema.json to new
sub-module qapi/misc.json, then include just the "misc" shard where
possible.

It's possible everywhere, except:

* monitor.c needs qmp-command.h to get qmp_init_marshal()

* monitor.c, ui/vnc.c and the generated qapi-event-FOO.c need
qapi-event.h to get enum QAPIEvent

Perhaps we'll get rid of those some other day.

Adding a type to qapi/migration.json now recompiles some 120 instead
of 2300 out of 5100 objects.

Backports commit 112ed241f5d9a411dbca92bdf597151cb853c6a7 from qemu
2018-03-09 10:23:27 -05:00
Markus Armbruster 5500a5e912
Include less of the generated modular QAPI headers
In my "build everything" tree, a change to the types in
qapi-schema.json triggers a recompile of about 4800 out of 5100
objects.

The previous commit split up qmp-commands.h, qmp-event.h, qmp-visit.h,
qapi-types.h. Each of these headers still includes all its shards.
Reduce compile time by including just the shards we actually need.

To illustrate the benefits: adding a type to qapi/migration.json now
recompiles some 2300 instead of 4800 objects. The next commit will
improve it further.

Backports commit 9af2398977a78d37bf184d6ff6bd04c72bfbf006 from qemu
2018-03-09 10:06:19 -05:00
Markus Armbruster fe90858609
qapi: Generate separate .h, .c for each module
Our qapi-schema.json is composed of modules connected by include
directives, but the generated code is monolithic all the same: one
qapi-types.h with all the types, one qapi-visit.h with all the
visitors, and so forth. These monolithic headers get included all
over the place. In my "build everything" tree, adding a QAPI type
recompiles about 4800 out of 5100 objects.

We wouldn't write such monolithic headers by hand. It stands to
reason that we shouldn't generate them, either.

Split up generated qapi-types.h to mirror the schema's modular
structure: one header per module. Name the main module's header
qapi-types.h, and sub-module D/B.json's header D/qapi-types-B.h.

Mirror the schema's includes in the headers, so that qapi-types.h gets
you everything exactly as before. If you need less, you can include
one or more of the sub-module headers. To be exploited shortly.

Split up qapi-types.c, qapi-visit.h, qapi-visit.c, qmp-commands.h,
qmp-commands.c, qapi-event.h, qapi-event.c the same way.
qmp-introspect.h, qmp-introspect.c and qapi.texi remain monolithic.

The split of qmp-commands.c duplicates static helper function
qmp_marshal_output_str() in qapi-commands-char.c and
qapi-commands-misc.c. This happens when commands returning the same
type occur in multiple modules. Not worth avoiding.

Since I'm going to rename qapi-event.[ch] to qapi-events.[ch], and
qmp-commands.[ch] to qapi-commands.[ch], name the shards that way
already, to reduce churn. This requires temporary hacks in
commands.py and events.py. Similarly, c_name() must temporarily
be taught to munge '/' in common.py. They'll go away with the rename.

Backports commit 252dc3105fc494182e236e97fe20f2d6b1d652cb from qemu
2018-03-09 09:54:36 -05:00
Markus Armbruster c18d107804
qapi/common: Fix guardname() for funny filenames
guardname() fails to return a valid C identifier for arguments
containing anything but [A-Za-z0-9_.-']. Fix that. Don't bother
protecting ticklish identifiers; header guards are all-caps, and no
ticklish identifiers are.

Backports commit f9c146399dabefb8cd13c9c467a9e710af15ea70 from qemu
2018-03-09 09:27:14 -05:00
Markus Armbruster 1fb1d31a1f
qapi/types qapi/visit: Generate built-in stuff into separate files
Linking code from multiple separate QAPI schemata into the same
program is possible, but involves some weirdness around built-in
types:

* We generate code for built-in types into .c only with option
--builtins. The user is responsible for generating code for exactly
one QAPI schema per program with --builtins.

* We generate code for built-in types into .h regardless of
--builtins, but guarded by #ifndef QAPI_VISIT_BUILTIN. Because all
copies of this code are exactly the same, including any combination
of these headers works.

Replace this contraption by something more conventional: generate code
for built-in types into their very own files: qapi-builtin-types.c,
qapi-builtin-visit.c, qapi-builtin-types.h, qapi-builtin-visit.h, but
only with --builtins. Obey --output-dir, but ignore --prefix for
them.

Make qapi-types.h include qapi-builtin-types.h. With multiple
schemata you now have multiple qapi-types.[ch], but only one
qapi-builtin-types.[ch]. Same for qapi-visit.[ch] and
qapi-builtin-visit.[ch].

Bonus: if all you need is built-in stuff, you can include a much
smaller header. To be exploited shortly.

Backports commit cdb6610ae4283720037bae2af1f78bd40eb5fe71 from qemu
2018-03-09 09:25:59 -05:00
Markus Armbruster b882e705dc
qapi: Make code-generating visitors use QAPIGen more
The use of QAPIGen is rather shallow so far: most of the output
accumulation is not converted. Take the next step: convert output
accumulation in the code-generating visitor classes. Helper functions
outside these classes are not converted.

Backports commit 71b3f0459c460c9e16a47372ccddbfa6e2c7aadf from qemu
2018-03-09 09:11:28 -05:00
Markus Armbruster 58246ea9d9
qapi: Record 'include' directives in intermediate representation
The include directive permits modular QAPI schemata, but the generated
code is monolithic all the same. To permit generating modular code,
the front end needs to pass more information on inclusions to the back
ends. The commit before last added the necessary information to the
parse tree. This commit adds it to the intermediate representation
and its QAPISchemaVisitor. A later commit will use this to to
generate modular code.

New entity QAPISchemaInclude represents inclusions. Call new visitor
method visit_include() for it, so visitors can see the sub-modules a
module includes.

Note that unlike other entities, QAPISchemaInclude has no name, and is
therefore not added to entity_dict.

New QAPISchemaEntity attribute @module names the entity's source file.
Call new visitor method visit_module() when it changes during a visit,
so visitors can keep track of the module being visited.

Backports commit cf40a0a5c2e1091846974cc8cc95a60e0b1db4af from qemu
2018-03-09 09:03:17 -05:00
Markus Armbruster 6fe71ebc68
qapi: Generate in source order
The generators' conversion to visitors (merge commit 9e72681d16)
changed the processing order of entities from source order to
alphabetical order. The next commit needs source order, so change it
back.

Backports commit 8a84767cc4f7e00e5dd62435c32be9e7d2cbe4d3 from qemu
2018-03-09 09:01:16 -05:00
Markus Armbruster cad1593b7d
qapi: Record 'include' directives in parse tree
The parse tree is a list of expressions. Except include expressions
currently get replaced by the included file's parse tree.

Instead of throwing away the include expression, keep it with the file
name expanded so you don't have to track the including file's
directory to make sense of it.

A future commit will put this include expression to use.

Backports commit 97f0249474d19c1d60fb9d934c8bc08625a619ca from qemu
2018-03-09 08:58:49 -05:00
Markus Armbruster 07453b11b8
qapi: Concentrate QAPISchemaParser.exprs updates in .__init__()
Backports commit 4257053083775c1f670fa828003915e25d13e9d7 from qemu
2018-03-09 08:56:45 -05:00
Markus Armbruster aaa4a812ed
qapi: Lift error reporting from QAPISchema.__init__() to callers
Backports commit 181feaf3555136dd7883e2434c4498ca1939bf1a from qemu
2018-03-09 08:55:45 -05:00
Markus Armbruster b859a59f49
qapi/common: Eliminate QAPISchema.exprs
Backports commit 71a7510baf8a5745eb844ab289f007ff8bbbee41 from qemu
2018-03-09 08:54:20 -05:00
Markus Armbruster 3ab06081d4
qapi: Improve include file name reporting in error messages
Error messages print absolute file names of included files even if the
user gave a relative one on the command line:

$ PYTHONPATH=scripts python -B tests/qapi-schema/test-qapi.py tests/qapi-schema/include-cycle.json
In file included from tests/qapi-schema/include-cycle.json:1:
In file included from /work/armbru/qemu/tests/qapi-schema/include-cycle-b.json:1:
/work/armbru/qemu/tests/qapi-schema/include-cycle-c.json:1: Inclusion loop for include-cycle.json

Improve this to

In file included from tests/qapi-schema/include-cycle.json:1:
In file included from tests/qapi-schema/include-cycle-b.json:1:
tests/qapi-schema/include-cycle-c.json:1: Inclusion loop for include-cycle.json

The error message when an include file can't be opened prints the
include directive's file name, which is relative to the including
file. Change this to print the file name relative to the working
directory. Visible in tests/qapi-schema/include-no-file.err.

Backports commit af97502ce9c648ae5c746b9e562d6e4586f02eee from qemu
2018-03-09 08:53:00 -05:00
Markus Armbruster d74daa8fce
qapi: Touch generated files only when they change
A massive number of objects depends on QAPI-generated headers. In my
"build everything" tree, it's roughly 4800 out of 5100. This is
particularly annoying when only some of the generated files change,
say for a doc fix.

Improve qapi-gen.py to touch its output files only if they actually
change. Rebuild time for a QAPI doc fix drops from many minutes to a
few seconds. Rebuilds get faster for certain code changes, too. For
instance, adding a simple QMP event now recompiles less than 200
instead of 4800 objects. But adding a QAPI type is as bad as ever;
we've clearly got more work to do.

Backports commit 907b846653fb3757bf2ab98d6d66f92df34d875f from qemu
2018-03-09 08:51:14 -05:00
Markus Armbruster 3b1d4defe3
qapi-gen: Convert from getopt to argparse
argparse is nicer to use than getopt, and gives us --help almost for
free.

Backports commit 3b446a1817289d89844ad77c719bdc44bbcd1198 from qemu
2018-03-09 08:49:33 -05:00
Markus Armbruster 8c51980332
qapi-gen: New common driver for code and doc generators
Whenever qapi-schema.json changes, we run six programs eleven times to
update eleven files. Similar for qga/qapi-schema.json. This is
silly. Replace the six programs by a single program that spits out
all eleven files.

The programs become modules in new Python package qapi, along with the
helper library. This requires moving them to scripts/qapi/. While
moving them, consistently drop executable mode bits.

Backports commit fb0bc835e56b894cbc7236294921e5393c786ad8 from qemu
2018-03-09 08:47:12 -05:00
Markus Armbruster 8d713d6e47
qapi: Turn generators into modules
The next commit will introduce a common driver program for all
generators. The generators need to be modules for that. qapi2texi.py
already is. Make the other generators follow suit.

The changes are actually trivial. Obvious in the diffs once you view
them with whitespace changes ignored.

Backports commit 26df4e7fab06422b21e11d039c64243ca4003147 from qemu
2018-03-09 08:02:35 -05:00
Markus Armbruster b97d1f98ae
qapi: Reduce use of global variables in generators some
In preparation of the next commit, which will turn the generators into
modules. These global variables will become local to main() then.

Backports commit 93b564c444edc41901d0f7e922833eeb751f8249 from qemu
2018-03-09 07:58:03 -05:00
Markus Armbruster 03c3b81d7a
qapi: New classes QAPIGenC, QAPIGenH, QAPIGenDoc
These classes encapsulate accumulating and writing output.

Convert C code generation to QAPIGenC and QAPIGenH. The conversion is
rather shallow: most of the output accumulation is not converted.
Left for later.

The indentation machinery uses a single global variable indent_level,
even though we generally interleave creation of a .c and its .h. It
should become instance variable of QAPIGenC. Also left for later.

Documentation generation isn't converted, and QAPIGenDoc isn't used.
This will change shortly.

Backports commit 47a6ea9aab1d857015684cda387ffba05a036721 from qemu
2018-03-09 07:54:40 -05:00
Markus Armbruster 3fe150978c
qapi: Rename variable holding the QAPISchemaGenFOOVisitor
Rename the variable holding the QAPISchemaGenFOOVisitor from gen to
vis, to avoid confusion in the next commit.

Backports commit d46eec4260540d83bafba91608842ab03dabf339 from qemu
2018-03-09 07:47:22 -05:00
Markus Armbruster b03a71e1e4
qapi: Generate up-to-date copyright notice
Each generator carries a copyright notice for the generator itself,
and another one for the files it generates. Only the former have been
updated along the way, the latter have not, and are all out of date.

Fix by copying the generator's copyright notice to the generated files
instead. Note that the fix doesn't copy the "Authors:" part; the
generated files' outdated Authors list goes away without replacement.

Backports commit 5ddeec83eb0284b52bb3d496a49ba1657069ed45 from qemu
2018-03-09 07:43:00 -05:00
Markus Armbruster 42f64cc962
qapi: Streamline boilerplate comment generation
Every generator has separate boilerplate for .h and .c, and their
differences are boring. All of them repeat the license note.

Reduce the repetition as follows. Move common text like the license
note to common open_output(), next to the existing common text there.
For each generator, replace the two separate descriptions by a single
one.

While there, emit an "automatically generated" note into generated
documentation, too.

Backports commit c263de3f419be945499ff7e6bd7512702f8bd522 from qemu
2018-03-09 07:40:58 -05:00
KONRAD Frederic 4b9a1ceb4a
sparc: fix leon3 casa instruction when MMU is disabled
Since the commit af7a06bac7d3abb2da48ef3277d2a415772d2ae8:
`casa [..](10), .., ..` (and probably others alternate space instructions)
triggers a data access exception when the MMU is disabled.

When we enter get_asi(...) dc->mem_idx is set to MMU_PHYS_IDX when the MMU
is disabled. Just keep mem_idx unchanged in this case so we passthrough the
MMU when it is disabled.

Backports commit 6e10f37c86068e35151f982c976a85f1bec07ef2 from qemu
2018-03-09 01:39:53 -05:00
Laurent Vivier 9e72ef3b52
target/m68k: add fscale, fgetman and fgetexp
Using local m68k floatx80_getman(), floatx80_getexp(), floatx80_scale()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

Backports commit 0d379c1709aa6b2d09dd3b493bfdf3a5fe6debcd from qemu
2018-03-09 01:37:34 -05:00
Laurent Vivier 5fa3a97549
softfloat: use floatx80_infinity in softfloat
Since f3218a8 ("softfloat: add floatx80 constants")
floatx80_infinity is defined but never used.

This patch updates floatx80 functions to use
this definition.

This allows to define a different default Infinity
value on m68k: the m68k FPU defines infinity with
all bits set to zero in the mantissa.

Backports commit 0f605c889ca3fe9744166ad4149d0dff6dacb696 from qemu
2018-03-09 01:34:45 -05:00
Laurent Vivier 08c03a5de4
target/m68k: add fmod/frem
Using a local m68k floatx80_mod()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]

The quotient byte of the FPSR is updated with
the result of the operation.

Backports commit 591596b77a1872d0652e666271ca055e57ea1e21 from qemu
2018-03-09 01:28:58 -05:00
Laurent Vivier b42fcb5496
softfloat: export some functions
Move fpu/softfloat-macros.h to include/fpu/

Export floatx80 functions to be used by target floatx80
specific implementations.

Exports:
propagateFloatx80NaN(), extractFloatx80Frac(),
extractFloatx80Exp(), extractFloatx80Sign(),
normalizeFloatx80Subnormal(), packFloatx80(),
roundAndPackFloatx80(), normalizeRoundAndPackFloatx80()

Also exports packFloat32() that will be used to implement
m68k fsinh, fcos, fsin, ftan operations.

Backports commit 88857aca93f6ec8f372fb9c8201394b0e5582034 from qemu
2018-03-09 01:22:00 -05:00
Laurent Vivier c0ab026e78
target/m68k: TCGv returned by gen_load() must be freed
Backports commit 24989f0e21cc9cd90237d4836a456c3ffb824b3e from qemu
2018-03-09 01:16:01 -05:00
Richard Henderson 81ae246f07
target/arm: Enable ARM_FEATURE_V8_FCMA
Enable it for the "any" CPU used by *-linux-user.

Backports commit e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078 from qemu
2018-03-09 01:12:19 -05:00
Richard Henderson 85cfb78ea2
target/arm: Decode t32 simd 3reg and 2reg_scalar extension
Happily, the bits are in the same places compared to a32.

Backports commit 0052087efb8a5c0e29ddc2f59f8476fcdc6495b2 from qemu
2018-03-09 01:11:14 -05:00
Richard Henderson e5da25aaf8
target/arm: Decode aa32 armv8.3 2-reg-index
Backports commit 638808ff8a0c0d62333822d3756e5d98f9f369c3 from qemu
2018-03-09 01:09:59 -05:00
Richard Henderson 69890ae145
target/arm: Decode aa32 armv8.3 3-same
Backports commit 8b7209fae730813d722b17a8a13b6a16c84616c8 from qemu
2018-03-09 01:08:26 -05:00
Richard Henderson abd86b2287
target/arm: Decode aa64 armv8.3 fcmla
Backports commit d17b7cdcf4ea3e858ceee8b86fc8544bb71561e6 from qemu

Also remember to commit vec_helper.
2018-03-09 01:05:02 -05:00
Richard Henderson 4b39a36416
target/arm: Decode aa64 armv8.3 fcadd
Backports commit 1695cd61b08d4376c11e0658836c4f08b4fc3aa1 from qemu
2018-03-09 00:58:37 -05:00
Richard Henderson 0b1ab3e745
target/arm: Add ARM_FEATURE_V8_FCMA
Not enabled anywhere yet.

Backports commit 0438f0372a7031debe796f4e3d30875d4d1e7899 from qemu
2018-03-09 00:28:37 -05:00
Richard Henderson fc74a022bf
target/arm: Enable ARM_FEATURE_V8_RDM
Enable it for the "any" CPU used by *-linux-user.

Backports commit f5dfc2ecdd48b71900bc50298ad2768d60356e44 from qemu
2018-03-09 00:27:34 -05:00
Richard Henderson 78b0b9c523
target/arm: Decode aa32 armv8.1 two reg and a scalar
Backports commit 61adacc8f589539ac6b25cfcbd6e099357188974 from qemu
2018-03-09 00:24:14 -05:00
Richard Henderson ca4ceb2dd7
target/arm: Decode aa32 armv8.1 three same
Backports commit 36a719348a9744d17c6ef6bac01bcb5fcd279753 from qemu
2018-03-09 00:18:31 -05:00
Richard Henderson 152c9484bd
target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
Backports commit d345df7a3f1336ceb0537c1fa0a7261030426768 from qemu
2018-03-09 00:12:00 -05:00
Lioncash 12fd2cc113
target/arm: Decode aa64 armv8.1 three same extra 2018-03-09 00:10:09 -05:00
Richard Henderson 4f585f71fb
target/arm: Decode aa64 armv8.1 scalar three same extra
Backports commit d9061ec3d27eb940402a7eafee3fb77ce1146ad4 from qemu
2018-03-09 00:02:23 -05:00
Richard Henderson 774cbded7a
target/arm: Refactor disas_simd_indexed size checks
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.

Backports commit 449f264b1749ac0e59c58bbc2eacdb3dc302c2bf from qemu
2018-03-08 23:53:39 -05:00
Richard Henderson 1fd2644738
target/arm: Refactor disas_simd_indexed decode
Include the U bit in the switches rather than testing separately.

Backports commit 5f81b1de43259ed0969e62a7419ab9dd9da2c5c0 from qemu
2018-03-08 23:44:03 -05:00
Richard Henderson 109a777fd6
target/arm: Add ARM_FEATURE_V8_RDM
Not enabled anywhere yet.

Backports commit 1dc81c15418d9b174f59a1c6262eb3487f352c56 from qemu
2018-03-08 23:44:03 -05:00
Peter Maydell e917a1ac0e
target/arm: Add Cortex-M33
Add a Cortex-M33 definition. The M33 is an M profile CPU
which implements the ARM v8M architecture, including the
M profile Security Extension.

Backports commit c7b26382fee8b745c6e903c85281babf30c2cb7c from qemu
2018-03-08 23:44:03 -05:00
Peter Maydell bd606401dc
target/arm: Define init-svtor property for the reset secure VTOR value
The Cortex-M33 allows the system to specify the reset value of the
secure Vector Table Offset Register (VTOR) by asserting config
signals. In particular, guest images for the MPS2 AN505 board rely
on the MPS2's initial VTOR being correct for that board.
Implement a QEMU property so board and SoC code can set the reset
value to the correct value.

Backports commit 38e2a77c9d6876e58f45cabb1dd9a6a60c22b39e from qemu
2018-03-08 23:44:03 -05:00
Peter Maydell eb4796e965
target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 any CPU
Now we have implemented FP16 we can enable it for the "any" CPU.

Backports commit 969b389ee8ba84bc3f2e7ccfa993679fac410ad2 from qemu
2018-03-08 23:44:02 -05:00
Alex Bennée 6e41113897
arm/translate-a64: add all single op FP16 to handle_fp_1src_half
This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use
existing helpers to achieve this.

Backports commit c2c08713a6a5846bbe601d4d1b4f9708ba77efdc from qemu
2018-03-08 23:44:02 -05:00
Alex Bennée c6c8a1cccc
arm/translate-a64: implement simd_scalar_three_reg_same_fp16
This covers the encoding group:

Advanced SIMD scalar three same FP16

As all the helpers are already there it is simply a case of calling the
existing helpers in the scalar context.

Backports commit 7c93b7741b29b3ffda81a6e9525771b4409db99f from qemu
2018-03-08 23:44:02 -05:00
Alex Bennée dd29452046
arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
I only needed to do a little light re-factoring to support the
half-precision helpers.

Backports commit 5c36d89567cfd049a7c59ff219639f788225068f from qemu
2018-03-08 23:44:02 -05:00
Alex Bennée 8bbabd7eb3
arm/translate-a64: add FP16 FMOV to simd_mod_imm
Only one half-precision instruction has been added to this group.

Backports commit 70b4e6a445715519ae55179dc54f6e961ab30c27 from qemu
2018-03-08 23:43:52 -05:00
Alex Bennée b117df18df
arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
Backports commit c625ff95070e3ef96bd007de744e1d97c881efeb from qemu
2018-03-08 22:45:39 -05:00
Alex Bennée 068143595e
arm/helper.c: re-factor rsqrte and add rsqrte_f16
Much like recpe the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Backports commit d719cbc7641991d16b891ffbbfc3a16a04e37b9a from qemu

Also removes a load of symbols that seem unnecessary from the header_gen script
2018-03-08 22:42:04 -05:00
Alex Bennée fdb07713e6
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
Backports commit b96a54c7e5576bd35b7d00d37b7929d2892d8cac from qemu
2018-03-08 21:57:35 -05:00
Alex Bennée 6102a61b14
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
We go with the localised helper.

Backports commit 986950283837f697b35782b9ac3bc99fca614640 from qemu
2018-03-08 19:15:23 -05:00
Alex Bennée 4ea310c131
arm/translate-a64: add FP16 FRECPE
Now we have added f16 during the re-factoring we can simply call the
helper.

Backports commit fbd06e1e4b6566b4d727f9e553c819d034942f68 from qemu
2018-03-08 19:12:06 -05:00
Alex Bennée 5f3864c2c2
arm/helper.c: re-factor recpe and add recepe_f16
It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Backports commit 5eb70735af1c0b607bf2671a53aff3710cc1672f from qemu
2018-03-08 19:05:48 -05:00
Alex Bennée c590ff441c
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Backports commit 15f8a233c8c023dbc77b6fe6cd7c79eac9bee263 from qemu
2018-03-08 18:51:35 -05:00
Alex Bennée 7161c1ed52
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 2018-03-08 18:48:25 -05:00
Alex Bennée 8ac9e3cff2
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Backports commit 7d4dd1a73a023f75c893623710e43743501b318e from qemu
2018-03-08 18:32:36 -05:00
Alex Bennée 39a68548d1
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
This covers all the floating point convert operations.

Backports commit 2df581304193d70eaf0d22cf4cb4613f74b6e59b from qemu
2018-03-08 18:25:29 -05:00
Alex Bennée d5f002b39a
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
This adds the full range of half-precision floating point to integral
instructions.

Backports commit 6109aea2d954891027acba64a13f1f1c7463cfac from qemu
2018-03-08 18:21:58 -05:00
Alex Bennée 33eda0f5d4
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
This actually covers two different sections of the encoding table:

Advanced SIMD scalar two-register miscellaneous FP16
Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Backports commit 5d432be6fd6efe37833ac82623c3abd35117b421 from qemu
2018-03-08 18:14:04 -05:00
Alex Bennée 82ffaab7de
arm/translate-a64: add FP16 x2 ops for simd_indexed
A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.

Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.

Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 18:08:39 -05:00
Alex Bennée 38815b2901
arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.

Backports commit 5d265064cf30daaacce5a4ce9945fc573015fb5f from qemu
2018-03-08 15:56:20 -05:00
Alex Bennée c6fda07628
arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Backports commit 7a2c6e618156674cf9eac8bf36e79f674fbf974e from qemu
2018-03-08 15:50:56 -05:00
Alex Bennée 4b2577537b
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.

Backports commit 026e2d6ef74000afb9049f46add4b94f594c8fb3 from qemu
2018-03-08 15:47:34 -05:00
Alex Bennée a02b9b81a9
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu

Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0
2018-03-08 15:42:48 -05:00
Alex Bennée ba8df54753
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.

Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu
2018-03-08 12:59:37 -05:00
Alex Bennée 4a6a41d2c5
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 12:56:15 -05:00
Alex Bennée 2f850606e9
arm/translate-a64: initial decode for simd_three_reg_same_fp16
This is the initial decode skeleton for the Advanced SIMD three same
instruction group.

The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.

Backports commit 376e8d6cda985df31c8561db4b7ea365b6fe6f87 from qemu
2018-03-08 12:53:23 -05:00
Alex Bennée fe74abd307
arm/translate-a64: handle_3same_64 comment fix
We do implement all the opcodes.

Backports commit 3840d219b433507f04a685120ff770ce4e06c55d from qemu
2018-03-08 12:51:01 -05:00
Alex Bennée af75074fe7
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).

Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 12:49:30 -05:00
Alex Bennée 27d8d01566
target/arm/helper: pass explicit fpst to set_rmode
As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.

Backports commit 9b04991686785e18b18a36d193b68f08f7c91648 from qemu
2018-03-08 12:41:54 -05:00
Alex Bennée 996f38056f
target/arm/cpu.h: add additional float_status flags
Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Backports commit d81ce0ef2c4f1052fcdef891a12499eca3084db7 from qemu
2018-03-08 12:34:39 -05:00
Alex Bennée 348789d2e4
target/arm/cpu.h: update comment for half-precision values
Backports commit d0e69ea88f4e74212b29d9436143c5bcfd437757 from qemu
2018-03-08 12:29:47 -05:00
Alex Bennée a030564492
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
Backports commit 6ad4d6187563f069fe5f11c3c1c9ccec1f69c2b7 from qemu
2018-03-08 12:29:17 -05:00
Alex Bennée e56ed38819
include/exec/helper-head.h: support f16 in helper calls
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.

Backports commit 35737497008aeabce5dc381a41d3827bec486192 from qemu
2018-03-08 12:28:05 -05:00
Peter Maydell f4df29ca4f
target/arm: Fix register definitions for VMIDR and VMPIDR
The register definitions for VMIDR and VMPIDR have separate
reginfo structs for the AArch32 and AArch64 registers. However
the 32-bit versions are wrong:
* they use offsetof instead of offsetoflow32 to mark where
the 32-bit value lives in the uint64_t CPU state field
* they don't mark themselves as ARM_CP_ALIAS

In particular this means that if you try to use an Arm guest CPU
which enables EL2 on a big-endian host it will assert at reset:
target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue == newvalue' failed.

because the reset of the 32-bit register writes to the top
half of the uint64_t.

Correct the errors in the structures.

Backports commit 36476562d57a3b64bbe86db26e63677dd21907c5 from qemu
2018-03-08 12:26:09 -05:00
Alex Bennée 283abedc68
fpu/softfloat: re-factor sqrt
This is a little bit of a departure from softfloat's original approach
as we skip the estimate step in favour of a straight iteration. There
is a minor optimisation to avoid calculating more bits of precision
than we need however this still brings a performance drop, especially
for float64 operations.

Backports commit c13bb2da9eedfbc5886c8048df1bc1114b285fb0 from qemu
2018-03-08 12:23:54 -05:00
Alex Bennée e2fb4b40c3
fpu/softfloat: re-factor compare
The compare function was already expanded from a macro. I keep the
macro expansion but move most of the logic into a compare_decomposed.

Backports commit 0c4c90929143a530730e2879204a55a30bf63758 from qemu
2018-03-08 12:21:20 -05:00
Alex Bennée c38b64f8a9
fpu/softfloat: re-factor minmax
Let's do the same re-factor treatment for minmax functions. I still
use the MACRO trick to expand but now all the checking code is common.

Backports commit 89360067071b1844bf745682e18db7dde74cdb8d from qemu
2018-03-08 12:18:35 -05:00
Alex Bennée 9b296329f6
fpu/softfloat: re-factor scalbn
This is one of the simpler manipulations you could make to a floating
point number.

Backports commit 0bfc9f195209593e91a98cf2233753f56a2e5c02 from qemu
2018-03-08 12:16:19 -05:00
Alex Bennée b389a8c7c4
fpu/softfloat: re-factor int/uint to float
These are considerably simpler as the lower order integers can just
use the higher order conversion function. As the decomposed fractional
part is a full 64 bit rounding and inexact handling comes from the
pack functions.

Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 12:13:09 -05:00
Alex Bennée acb4b1d5b1
fpu/softfloat: re-factor float to int/uint
We share the common int64/uint64_pack_decomposed function across all
the helpers and simply limit the final result depending on the final
size.

Backports commit ab52f973a504f8de0c5df64631ba4caea70a7d9e from qemu
2018-03-08 12:07:20 -05:00
Alex Bennée b82253adce
fpu/softfloat: re-factor round_to_int
We can now add float16_round_to_int and use the common round_decomposed and
canonicalize functions to have a single implementation for
float16/32/64 round_to_int functions.

Backports commit dbe4d53a590f5689772b683984588b3cf6df163e from qemu
2018-03-08 11:56:59 -05:00
Alex Bennée d92d5c6910
fpu/softfloat: re-factor muladd
We can now add float16_muladd and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 muladd functions.

Backports commit d446830a3aac33e7221e361dad3ab1e1892646cb from qemu
2018-03-08 10:55:40 -05:00
Alex Bennée 5ea008e178
fpu/softfloat: re-factor div
We can now add float16_div and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 versions.

Backports commit cf07323d494f4bc225e405688c2e455c3423cc40 from qemu
2018-03-08 10:25:07 -05:00
Alex Bennée 2bb86e1efc
fpu/softfloat: re-factor mul
We can now add float16_mul and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 versions.

Backports commit 74d707e2cc1e406068acad8e5559cd2584b1073a from qemu
2018-03-08 10:21:15 -05:00
Alex Bennée 58defd9bc0
fpu/softfloat: re-factor add/sub
We can now add float16_add/sub and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 add and sub functions.

Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 10:17:41 -05:00
Alex Bennée b1884d0685
fpu/softfloat: re-factor add/sub
We can now add float16_add/sub and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 add and sub functions.

Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 10:13:14 -05:00
Alex Bennée d80f1ea222
fpu/softfloat: define decompose structures
These structures pave the way for generic softfloat helper routines
that will operate on fully decomposed numbers.

Backports commit a90119b5a2c174250601be6503b91e5c9df6e83b from qemu
2018-03-08 10:06:25 -05:00
Alex Bennée 562f14adcc
fpu/softfloat: move the extract functions to the top of the file
This is pure code-motion during re-factoring as the helpers will be
needed earlier.

Backports commit d97544c94a37371347402bcbee19dd3748d70e48 from qemu
2018-03-08 10:04:54 -05:00
Alex Bennée b5fdc7b411
fpu/softfloat: improve comments on ARM NaN propagation
Mention the pseudo-code fragment from which this is based.

Backports commit 13894527f522caab4ec74334191ef29af975e521 from qemu
2018-03-08 10:03:32 -05:00
Alex Bennée 6eb4594f98
include/fpu/softfloat: add some float16 constants
This defines the same set of common constants for float 16 as defined
for 32 and 64 bit floats. These are often used by target helper
functions. I've also removed constants that are not used by anybody.

Backports commit efd4829edfa036c5506a16d05c91268faa1f6332 from qemu
2018-03-08 10:02:26 -05:00
Alex Bennée d14a090e65
include/fpu/softfloat: implement float16_set_sign helper
Backports commit 78b5a3e653c90b56ba650f54c07fc18f7b7bd905 from qemu
2018-03-08 10:01:30 -05:00
Alex Bennée 380699fa35
include/fpu/softfloat: implement float16_chs helper
Backports commit 5f10aef521427b3909c24a0c7a82839b43f876e2 from qemu
2018-03-08 10:01:03 -05:00
Alex Bennée facbc9ef66
include/fpu/softfloat: implement float16_abs helper
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.

Backports commit 28136775cd99c628f7d7c642b04eb87f062efef8 from qemu
2018-03-08 10:00:30 -05:00
Alex Bennée 0eee5afd0e
target/*/cpu.h: remove softfloat.h
As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do need types it's typically for float_status and
the rounding modes so we move that to softfloat-types.h as well.

As a result of not having softfloat in every cpu.h call we now need to
add it to various helpers that do need the full softfloat.h
definitions.

Backports commit 24f91e81b65fcdd0552d1f0fcb0ea7cfe3829c19 from qemu
2018-03-08 09:58:47 -05:00
Alex Bennée 2a078de5e1
fpu/softfloat-types: new header to prevent excessive re-builds
The main culprit here is bswap.h which pulled in softfloat.h so it
could use the types in its CPU_Float* and ldfl/stfql functions. As
bswap.h is very widely included this added a compile dependency every
time we touch softfloat.h. Move the typedefs for each float type into
their own file so we don't re-build the world every time we tweak the
main softfloat.h header.

Backports commit cfd88fc6f2722def193f5ef271381d8f6e2a2526 from qemu
2018-03-08 09:52:15 -05:00
Alex Bennée a34718da64
include/fpu/softfloat: remove USE_SOFTFLOAT_STRUCT_TYPES
It's not actively built and when enabled things fail to compile. I'm
not sure the type-checking is really helping here. Seeing as we "own"
our softfloat now lets remove the cruft.

Backports commit a9579fff616563ca34977af68c9646c8f7be1120 from qemu
2018-03-08 09:45:35 -05:00
Alex Bennée 8110bc8264
fpu/softfloat: implement float16_squash_input_denormal
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.

Backports commit 210cbd4910ae9e41e0a1785b96890ea2c291b381 from qemu
2018-03-08 09:44:20 -05:00
Peter Maydell 19baeb5120
target/arm: Implement v8M MSPLIM and PSPLIM registers
The v8M architecture includes hardware support for enforcing
stack pointer limits. We don't implement this behaviour yet,
but provide the MSPLIM and PSPLIM stack pointer limit registers
as reads-as-written, so that when we do implement the checks
in future this won't break guest migration.

Backports commit 57bb31568114023f67680d6fe478ceb13c51aa7d from qemu
2018-03-08 09:42:04 -05:00
Peter Maydell 5812f7e3a3
target/arm: Implement writing to CONTROL_NS for v8M
In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.

Backports commit 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f from qemu
2018-03-08 09:39:43 -05:00
Peter Maydell 09cfe29d5b
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.

Backports register related changes in commit 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b from qemu
2018-03-08 09:36:59 -05:00
Peter Maydell c390c07ae0
hw/intc/armv7m_nvic: Implement cache ID registers
M profile cores have a similar setup for cache ID registers
to A profile:
* Cache Level ID Register (CLIDR) is a fixed value
* Cache Type Register (CTR) is a fixed value
* Cache Size ID Registers (CCSIDR) are a bank of registers;
which one you see is selected by the Cache Size Selection
Register (CSSELR)

The only difference is that they're in the NVIC memory mapped
register space rather than being coprocessor registers.
Implement the M profile view of them.

Since neither Cortex-M3 nor Cortex-M4 implement caches,
we don't need to update their init functions and can leave
the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.
Newer cores (like the Cortex-M33) will want to be able to
set these ID registers to non-zero values, though.

Backports commit 43bbce7fbef22adf687dd84934fd0b2f8df807a8 from qemu
2018-03-08 09:35:53 -05:00
Peter Maydell 6f31c219b9
hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Instead of hardcoding the values of M profile ID registers in the
NVIC, use the fields in the CPU struct. This will allow us to
give different M profile CPU types different ID register values.

This commit includes the addition of the missing ID_ISAR5,
which exists as RES0 in both v7M and v8M.

(The values of the ID registers might be wrong for the M4 --
this commit leaves the behaviour there unchanged.)

Backports commit 5a53e2c1dc939fea1af92cc126ee546d8211d412 from qemu
2018-03-08 09:34:37 -05:00
Richard Henderson 1f71084740
target/arm: Handle SVE registers when using clear_vec_high
When storing to an AdvSIMD FP register, all of the high
bits of the SVE register are zeroed. Therefore, call it
more often with is_q as a parameter.

Backports commit 4ff55bcb0ee6452b768835f86d94bd727185f812 from qemu
2018-03-08 09:32:33 -05:00
Richard Henderson 07b928eca4
target/arm: Enforce access to ZCR_EL at translation
This also makes sure that we get the correct ordering of
SVE vs FP exceptions.

Backports commit 490aa7f13a2ad31f92205879c4dc2387b602ef14 from qemu
2018-03-08 09:17:33 -05:00
Richard Henderson c095dc9e83
target/arm: Suppress TB end for FPCR/FPSR
Nothing in either register affects the TB.

Backports commit b916c9c35ce8158bf7f9ed5514eb279e52875de2 from qemu
2018-03-08 09:15:02 -05:00
Richard Henderson d5c4d3e3c3
target/arm: Enforce FP access to FPCR/FPSR
Backports commit fe03d45f9e9baa89e8c4da50de771767d5d48990 from qemu
2018-03-08 09:14:52 -05:00
Richard Henderson 1bff556dbc
target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.

Backports commit 5d1e699988cdb1494ab4ac9a2b67d4c539143654 from qemu
2018-03-08 09:06:46 -05:00
Paolo Bonzini c88064b52c
memory: remove memory_region_test_and_clear_dirty
It is unused after g364fb has been converted to use DirtyBitmapSnapshot.

Backports commit 77302fb5df05ffca9f41b5b54e3b67c601719d57 from qemu
2018-03-08 09:02:06 -05:00
Marc-André Lureau 372766d6d3
build-sys: check static linking of UBSAN
Backports commit 218bb57dd79d6843e0592c30a82ea8c1fddc74a5 from qemu
2018-03-08 09:00:31 -05:00
Marc-André Lureau bb442e7843
build-sys: remove useless extra*flags variables
Only EXTRA_LDFLAGS seems to be used during configure Xen checks.

Backports commit 1de19951f11e5b9935b2dccffd962382429a5e29 from qemu
2018-03-08 08:59:40 -05:00
Daniel P. Berrange 7d4286cda7
Revert "build-sys: silence make by default or V=0"
This reverts commit 42a77f1ce4934b243df003f95bda88530631387a.

The primary intention of this change was to silence messages
like

make[1]: '/home/berrange/src/virt/qemu/capstone/libcapstone.a' is up to date.

which we get when calling make recursively with explicit
targets.

The problem is that this change affected every make target,
not merely the targets that triggered these "is up to date"
messages. As a result any targets that were not invoking
commands via "$(call quiet-command ...)" suddenly become
silent. This is particularly bad for "make install" which
now appears todo nothing.

Rather than go through every make rule and try to identify
places where we now need to explicitly print a message to
show work taking place, just revert the change.

To address the original problem of silencing "is up to date"
messages, we simply add --quiet to the SUBDIR_MAKEVARS
variable, so it only affects us on recursive make calls.

Backports commit 8cc357b5a8dfba8ed11d1ce376afbc4ea35677a9 from qemu
2018-03-08 08:58:11 -05:00
Andreas Gustafsson 53dd82a7ca
oslib-posix: check for posix_memalign in configure script
Check for the presence of posix_memalign() in the configure script,
not using "defined(_POSIX_C_SOURCE) && !defined(__sun__)". This
lets qemu use posix_memalign() on NetBSD versions that have it,
instead of falling back to valloc() which is wasteful when the
required alignment is smaller than a page.

Backports commit 9bc5a7193fb422ee53187601eba577ee5d195522 from qemu
2018-03-08 08:56:35 -05:00
Markus Armbruster 6a71ff06ca
Include qapi/qmp/qdict.h exactly where needed
This cleanup makes the number of objects depending on qapi/qmp/qdict.h
drop from 4550 (out of 4743) to 368 in my "build everything" tree.
For qapi/qmp/qobject.h, the number drops from 4552 to 390.

While there, separate #include from file comment with a blank line.

Backports commit 452fcdbc49c59884c8c284268d64baa24fea11e1 from qemu
2018-03-08 08:51:46 -05:00
Markus Armbruster 1496dddeab
Include qapi/qmp/qlist.h exactly where needed
This cleanup makes the number of objects depending on qapi/qmp/qlist.h
drop from 4551 (out of 4743) to 16 in my "build everything" tree.

While there, separate #include from file comment with a blank line.

Backports commit 47e6b297e76007c04a1e9c492006fe093d932cd9 from qemu
2018-03-08 08:50:06 -05:00
Markus Armbruster 801dbfce3d
Include qapi/qmp/qobject.h exactly where needed
Backports commit 5ee9d2fe9e1e15d6e4a112220da3ad8a3512819b from qemu
2018-03-08 08:48:27 -05:00
Max Reitz b98c4d24d1
qapi: Add qobject_is_equal()
This generic function (along with its implementations for different
types) determines whether two QObjects are equal.

Backports commit b38dd678a21582e03ecd2dec76ccf8290455628a from qemu
2018-03-08 08:41:43 -05:00
Max Reitz e42e3307f7
qapi/qnull: Add own header
Backports commit 84be629d5545b5ccc5bff2824e4288677e27de9c from qemu
2018-03-08 08:35:23 -05:00
Markus Armbruster f89de73110
qdict qlist: Make most helper macros functions
The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need
qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h
and qnum.h in the headers, but not qbool.h and qstring.h. Works,
because we include those wherever the macros get used.

Open-coding these helpers is of dubious value. Turn them into
functions and drop the includes from the headers.

This cleanup makes the number of objects depending on qapi/qmp/qnum.h
from 4551 (out of 4743) to 46 in my "build everything" tree. For
qapi/qmp/qnull.h, the number drops from 4552 to 21.

Backports commit 15280c360e54a65e2c7be1a47bfbe41dce1ef986 from qemu
2018-03-08 08:30:10 -05:00
Igor Mammedov 5a66d7f326
sparc: move adhoc CPUSPARCState initialization to realize time
SPARCCPU::env was initialized from previously set properties
(with help of sparc_cpu_parse_features) in cpu_sparc_register().
However there is not reason to keep it there as this task is
typically done at realize time. So move post properties
initialization into sparc_cpu_realizefn, which brings
cpu_sparc_init() closer to cpu_generic_init().

Backports commit 700549620b3ee15924f19b9eb79961655ce671c5 from qemu
2018-03-07 21:40:33 -05:00
Igor Mammedov 0d7be1a913
sparc: embed sparc_def_t into CPUSPARCState
Make CPUSPARCState::def embedded so it would be allocated as part
of cpu instance and we won't have to worry about cleaning def pointer
up mannualy on cpu destruction.

Backports commit 576e1c4c239621482474ba7b495a41bab2d16ae5 from qemu
2018-03-07 21:35:23 -05:00
Igor Mammedov 2142f3ff98
sparc: convert cpu models to SPARC cpu subclasses
Backports commit 12a6c15ef31c98ecefa63e91ac36955383038384 from qemu
2018-03-07 21:30:22 -05:00
Marc-André Lureau 2caf90cb2b
qlit: Tighten QLit list vs QList comparison
We check that all members of the QLit list are also in the QList. We
neglect to check the other direction. Fix that.

While there, use QLIST_FOREACH_ENTRY() to simplify the code and break
the loop on the first mismatch.

Backports commit cbb654052600c376d5ee3401c98a25d09d11a154 from qemu
2018-03-07 21:10:40 -05:00
Marc-André Lureau b7aa91bc5c
qlit: Tighten QLit dict vs QDict comparison
We check that all members of the QLit dictionary are also in the
QDict. We neglect to check the other direction.

Comparing the number of members suffices, because QDict can't
contain duplicate members, and putting duplicates in a QLit is a
programming error.

Backports commit 6da8a7a3b444211914418d2b3c7dc615d70a7d2d from qemu
2018-03-07 21:09:22 -05:00
Marc-André Lureau c1ad032a88
qlit: Replace open-coded qnum_get_int() by call
Bonus: rids us of a side effect in an assertion.

Backports commit 5f4bd8093671962093d9ec7d57ef65244b270dd4 from qemu
2018-03-07 17:22:06 -05:00
Marc-André Lureau bc2ffe2a71
qlit: add QLIT_QNULL and QLIT_BOOL
As they are going to be used in the following patches.

Backports commit 6c6084c1b0802f5265d5c7dc27f7125d9fd1cceb from qemu
2018-03-07 17:18:56 -05:00
Marc-André Lureau 2833ad4f4c
qlit: make qlit_equal_qobject() take const arguments
Backports commit e2346a19521c6cce417250c75adb0b3a7cd5535a from qemu
2018-03-07 17:17:38 -05:00
Marc-André Lureau 966cac10a7
qlit: make qlit_equal_qobject return a bool
Make it more obvious about the expected return values.

Backports commit d9eba57a6ad6d8fe8cf11bdd8345bbda66deb6d9 from qemu
2018-03-07 17:16:34 -05:00
Marc-André Lureau c51622c4ce
qlit: rename compare_litqobj_to_qobj() to qlit_equal_qobject()
compare_litqobj_to_qobj() lacks a qlit_ prefix. Moreover, "compare"
suggests -1, 0, +1 for less than, equal and greater than. The
function actually returns non-zero for equal, zero for unequal.
Rename to qlit_equal_qobject().

Its return type will be cleaned up in the next patch.

Backports commit 60cc2eb7afd40b9cbaa35a5e0b54f365ac6e49f1 from qemu
2018-03-07 17:14:55 -05:00
Marc-André Lureau b462c3929f
qlit: Change compound literals to initializers
The QLIT_QFOO() macros expand into compound literals. Sadly, gcc
doesn't recognizes these as constant expressions (clang does), which
makes the macros useless for initializing objects with static storage
duration.

There is a gcc bug about it:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71713

Change the macros to expand into initializers.

Backports commit d5cd8fbf130312bea91823c41de87d55818d599b from qemu
2018-03-07 17:13:14 -05:00
Marc-André Lureau a5d527ca72
qlit: use QLit prefix consistently
Rename from LiteralQ to QLit.

Backports commit 082696e767db4d2b6c8c8c233d28291b83fc2b21 from qemu
2018-03-07 17:10:26 -05:00
Marc-André Lureau c85b87fe06
qlit: move qlit from check-qjson to qobject/
Fix code style issues while at it, to please checkpatch.

Backports commit 28035bcdf4647245743cf87cea3788331bf67a5f from qemu
2018-03-07 17:08:17 -05:00
Marc-André Lureau 101f763077
qdict: Add qdict_put_null() helper, and put it to use
Backports relevant parts of commit 0f9afc2a8b5e78e511d79c936aa7b36deb3508bf from qemu
2018-03-07 17:00:41 -05:00
Markus Armbruster e1a055bd73
qobject: Explain how QNum works, and why
Backports commit f90cb2846a0b167d47131ba4600dcc816bccb1c6 from qemu
2018-03-07 16:58:46 -05:00
Eduardo Habkost 9d412ac4b3
qapi: Fix error handling code on alternate conflict
The conflict check added by commit c0644771 ("qapi: Reject
alternates that can't work with keyval_parse()") doesn't work
with the following declaration:

{ 'alternate': 'Alt',
'data': { 'one': 'bool',
'two': 'str' } }

It crashes with:

Traceback (most recent call last):
File "./scripts/qapi-types.py", line 295, in <module>
schema = QAPISchema(input_file)
File "/home/ehabkost/rh/proj/virt/qemu/scripts/qapi.py", line 1468, in __init__
self.exprs = check_exprs(parser.exprs)
File "/home/ehabkost/rh/proj/virt/qemu/scripts/qapi.py", line 958, in check_exprs
check_alternate(expr, info)
File "/home/ehabkost/rh/proj/virt/qemu/scripts/qapi.py", line 830, in check_alternate
% (name, key, types_seen[qtype]))
KeyError: 'QTYPE_QSTRING'

This happens because the previously-seen conflicting member
('one') can't be found at types_seen[qtype], but at
types_seen['QTYPE_BOOL'].

Fix the bug by moving the error check to the same loop that adds
new items to types_seen, raising an exception if types_seen[qt]
is already set.

Backports commit fda72ab4510bcc680a3c4fe55997aa29589884f7 from qemu
2018-03-07 16:57:59 -05:00
Lioncash 49166d71ab
cpu:Remove unused callbacks 2018-03-07 16:55:46 -05:00
Markus Armbruster 615e361cf2
qapi: Introduce a first class 'null' type
I expect the 'null' type to be useful mostly for members of alternate
types.

Backports commit 4d2d5c41a9e8ee201cda8be8701f7f9fc92e71aa from qemu
2018-03-07 16:52:41 -05:00
Markus Armbruster 4a7abec7c9
qapi: Use QNull for a more regular visit_type_null()
Make visit_type_null() take an @obj argument like its buddies. This
helps keep the next commit simple.

Backports commit d2f95f4d482374485234790a6fc3cca29ebb7355 from qemu
2018-03-07 16:50:16 -05:00
Markus Armbruster 3fd0ff8aa7
qapi: Separate type QNull from QObject
Backports commit 006ca09f3027d86346fce707e9295975c6558f42 from qemu
2018-03-07 16:43:51 -05:00
Markus Armbruster 566b097b85
Eliminate qapi/qmp/types.h
qapi/qmp/types.h is a convenience header to include a number of
qapi/qmp/ headers. Since we rarely need all of the headers
qapi/qmp/types.h includes, we bypass it most of the time. Most of the
places that use it don't need all the headers, either.

Include the necessary headers directly, and drop qapi/qmp/types.h.

Backports commit 6b67395762a4c8b6ca94364e0a0f616a6470c46a from qemu
2018-03-07 12:39:23 -05:00
Markus Armbruster bbc9bcbb44
Typedef the subtypes of QObject in qemu/typedefs.h, too
This renders many inclusions of qapi/qmp/q*.h superfluous. They'll be
dropped in the next few commits.

Backports commit 9f5c734d591e26186a71f9e36d752f4798df3672 from qemu
2018-03-07 12:29:31 -05:00
Markus Armbruster 5d554fefeb
Include qapi/error.h exactly where needed
This cleanup makes the number of objects depending on qapi/error.h
drop from 1910 (out of 4743) to 1612 in my "build everything" tree.

While there, separate #include from file comment with a blank line,
and drop a useless comment on why qemu/osdep.h is included first.

Backports commit e688df6bc4549f28534cdb001f168b8caae55b0c from qemu
2018-03-07 12:26:38 -05:00
Markus Armbruster aa7a707738
Drop superfluous includes of qapi-types.h and test-qapi-types.h
Backports commit 522ece32d214bd4b086821c4350c2aebe5587878 from qemu
2018-03-07 12:21:43 -05:00
Pavel Dovgalyuk 01150e151e
m68k: implement movep instruction
This patch implements movep instruction. It moves data between a data register
and alternate bytes within the address space starting at the location
specified and incrementing by two.

It was designed for the original 68000 and used in firmwares for
interfacing the 8-bit peripherals through the 16-bit data bus.
Without this patch opcode for this instruction is recognized as some bitop.

Backports commit 1226e212292e271b8795265c9639d5c0553df199 from qemu
2018-03-07 11:51:32 -05:00
Peter Maydell 8e7ecd89a4
target/arm/translate.c: Fix missing 'break' for TT insns
The code where we added the TT instruction was accidentally
missing a 'break', which meant that after generating the code
to execute the TT we would fall through to 'goto illegal_op'
and generate code to take an UNDEF insn.

Backports commit 384c6c03fb687bea239a5990a538c4bc50fdcecb from qemu
2018-03-07 11:45:39 -05:00
Richard Henderson 02516c53ff
target/arm: Add SVE state to TB->FLAGS
Add both SVE exception state and vector length.

Backports commit 1db5e96c54d8b3d1df0a6fed6771390be6b010da from qemu
2018-03-07 11:44:32 -05:00
Richard Henderson 523e5114c0
target/arm: Add ZCR_ELx
Define ZCR_EL[1-3].

Backports commit 5be5e8eda78474f6e89a54af12ee6f44234115ed from qemu
2018-03-07 11:41:46 -05:00
Richard Henderson a47fb718bc
target/arm: Add predicate registers for SVE
Backports commit 3c7d30866fd1f56e5945726221410e0d8d535033 from qemu
2018-03-07 11:34:57 -05:00
Richard Henderson 834e3a1d04
target/arm: Expand vector registers for SVE
Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg.
The previous patches have made the change in representation
relatively painless.

Backports commit c39c2b9043ec59516c80f2c6f3e8193e99d04d4b from qemu
2018-03-07 11:33:49 -05:00
Lioncash 5439b4a542
unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers
Avoids directly touching the representation of the VFP/NEON/SIMD registers
2018-03-07 11:25:41 -05:00
Lioncash 9e14a824ed
unicorn/mips: Lessen the amount of MIPS_CPU macro usage
Syntaxically reduces line noise
2018-03-07 10:50:08 -05:00
Lioncash be260c43b6
unicorn/sparc: Lessen the use of the SPARC_CPU macro
Syntaxically reduces the amount of line noise
2018-03-07 10:46:18 -05:00
Lioncash 047766c908
unicorn/m68k: Lessen usage of M68K_CPU macro
Reduces the amount of line noise (and avoids syntaxically repeating accesses to the environment state)
2018-03-07 10:37:50 -05:00
Lioncash 6cbcf9ce76
unicorn/i386: Lessen amount of X86_CPU macros and casts
Reduces the amount of line noise
2018-03-07 10:34:00 -05:00
Lioncash 441f3b73da
unicorn_arm: Use ARM_CPU macro instead of a direct cast in arm_release
Makes the code more reliant on qemu instead of manually doing our own thing
2018-03-07 10:24:21 -05:00
Lioncash 767dedcb09
unicorn_aarch64: Clean up variable assignments in arm64_release 2018-03-07 10:22:51 -05:00
Lioncash d0abc23e99
unicorn/arm: use uc->cpu instead of uc->current_cpu
Keeps cpu variable usage consistent. Also eliminates unnecessary casts
2018-03-07 10:15:49 -05:00
Lioncash 890f234a53
unicorn/aarch64: Lessen the amount of ARMCPU macro usages
This macro can just be used once per function that it's used in,
reducing the overall amount of line noise in register reading and writing
2018-03-07 09:59:27 -05:00
Ard Biesheuvel f425b6aa81
target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support
Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
AArch64 user mode emulation.

Backports commit 955f56d44a73d74016b2e71765d984ac7a6db1dc from qemu
2018-03-07 08:58:43 -05:00
Ard Biesheuvel 85e6d710e4
target/arm: implement SM4 instructions
This implements emulation of the new SM4 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit b6577bcd251ca0d57ae1de149e3c706b38f21587 from qemu
2018-03-07 08:57:53 -05:00
Ard Biesheuvel 78d15a9cd0
target/arm: implement SM3 instructions
This implements emulation of the new SM3 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit 80d6f4c6bbb718f343a832df8dee15329cc7686c from qemu
2018-03-07 08:53:47 -05:00
Ard Biesheuvel 72078a7674
target/arm: implement SHA-3 instructions
This implements emulation of the new SHA-3 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit cd270ade74ea86467f393a9fb9c54c4f1148c28f from qemu
2018-03-07 08:44:47 -05:00
Ard Biesheuvel 66b8b01f09
target/arm: implement SHA-3 instructions
This implements emulation of the new SHA-3 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit cd270ade74ea86467f393a9fb9c54c4f1148c28f from qemu
2018-03-07 08:41:40 -05:00
Ard Biesheuvel 0ef74f6d6d
target/arm: implement SHA-512 instructions
This implements emulation of the new SHA-512 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit 90b827d131812d7f0a8abb13dba1942a2bcee821 from qemu
2018-03-07 08:39:49 -05:00
Peter Maydell c1f778a438
target/arm: Handle exceptions during exception stack pop
Handle possible MPU faults, SAU faults or bus errors when
popping register state off the stack during exception return.

Backports commit 95695effe8caa552b8f243bceb3a08de4003c882 from qemu
2018-03-07 08:33:21 -05:00
Peter Maydell 0dadc2575f
target/arm: Make exception vector loads honour the SAU
Make the load of the exception vector from the vector table honour
the SAU and any bus error on the load (possibly provoking a derived
exception), rather than simply aborting if the load fails.

Backports commit 600c33f24752a00e81e9372261e35c2befea612b from qemu
2018-03-07 08:31:57 -05:00
Peter Maydell 2c8a0fe0d7
nvic: Implement AIRCR changes for v8M
The Application Interrupt and Reset Control Register has some changes
for v8M:
 * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
   real state if the security extension is implemented and otherwise
   are constant
 * the PRIGROUP field is banked between security states
 * non-secure code can be blocked from using the SYSRESET bit
   to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.

Backports register-related additions in commit 3b2e934463121f06d04e4d17658a9a7cdc3717b0 from qemu
2018-03-07 08:30:34 -05:00
Peter Maydell 630a38cf94
target/arm: Make v7m_push_callee_stack() honour MPU
Make v7m_push_callee_stack() honour the MPU by using the
new v7m_stack_write() function. We return a flag to indicate
whether the pushes failed, which we can then use in
v7m_exception_taken() to cause us to handle the derived
exception correctly.

Backports commit 65b4234ff73a4d4865438ce30bdfaaa499464efa from qemu
2018-03-07 08:23:04 -05:00
Peter Maydell 0bc82ea78f
target/arm: Make v7M exception entry stack push check MPU
The memory writes done to push registers on the stack
on exception entry in M profile CPUs are supposed to
go via MPU permissions checks, which may cause us to
take a derived exception instead of the original one of
the MPU lookup fails. We were implementing these as
always-succeeds direct writes to physical memory.
Rewrite v7m_push_stack() to do the necessary checks.

Backports commit fd592d890ec40e3686760de84044230a8ebb1eb3 from qemu
2018-03-07 08:20:02 -05:00
Peter Maydell a10b65bd47
target/arm: Add ignore_stackfaults argument to v7m_exception_taken()
In the v8M architecture, if the process of taking an exception
results in a further exception this is called a derived exception
(for example, an MPU exception when writing the exception frame to
memory). If the derived exception happens while pushing the initial
stack frame, we must ignore any subsequent possible exception
pushing the callee-saves registers.

In preparation for making the stack writes check for exceptions,
add a return value from v7m_push_stack() and a new parameter to
v7m_exception_taken(), so that the former can tell the latter that
it needs to ignore failures to write to the stack. We also plumb
the argument through to v7m_push_callee_stack(), which is where
the code to ignore the failures will be.

(Note that the v8M ARM pseudocode structures this slightly differently:
derived exceptions cause the attempt to process the original
exception to be abandoned; then at the top level it calls
DerivedLateArrival to prioritize the derived exception and call
TakeException from there. We choose to let the NVIC do the prioritization
and continue forward with a call to TakeException which will then
take either the original or the derived exception. The effect is
the same, but this structure works better for QEMU because we don't
have a convenient top level place to do the abandon-and-retry logic.)

Backports commit 0094ca70e165cfb69882fa2e100d935d45f1c983 from qemu
2018-03-07 08:17:25 -05:00
Peter Maydell e1349f817a
target/arm: Split "get pending exception info" from "acknowledge it"
Currently armv7m_nvic_acknowledge_irq() does three things:
* make the current highest priority pending interrupt active
* return a bool indicating whether that interrupt is targeting
Secure or NonSecure state
* implicitly tell the caller which is the highest priority
pending interrupt by setting env->v7m.exception

We need to split these jobs, because v7m_exception_taken()
needs to know whether the pending interrupt targets Secure so
it can choose to stack callee-saves registers or not, but it
must not make the interrupt active until after it has done
that stacking, in case the stacking causes a derived exception.
Similarly, it needs to know the number of the pending interrupt
so it can read the correct vector table entry before the
interrupt is made active, because vector table reads might
also cause a derived exception.

Create a new armv7m_nvic_get_pending_irq_info() function which simply
returns information about the highest priority pending interrupt, and
use it to rearrange the v7m_exception_taken() code so we don't
acknowledge the exception until we've done all the things which could
possibly cause a derived exception.

Backports part of commit 6c9485188170e11ad31ce477c8ce200b8e8ce59d from qemu
2018-03-07 08:12:35 -05:00
Peter Maydell 49010633f0
target/arm: Add armv7m_nvic_set_pending_derived()
In order to support derived exceptions (exceptions generated in
the course of trying to take an exception), we need to be able
to handle prioritizing whether to take the original exception
or the derived exception.

We do this by introducing a new function
armv7m_nvic_set_pending_derived() which the exception-taking code in
helper.c will call when a derived exception occurs. Derived
exceptions are dealt with mostly like normal pending exceptions, so
we share the implementation with the armv7m_nvic_set_pending()
function.

Note that the way we structure this is significantly different
from the v8M Arm ARM pseudocode: that does all the prioritization
logic in the DerivedLateArrival() function, whereas we choose to
let the existing "identify highest priority exception" logic
do the prioritization for us. The effect is the same, though.

Backports part of commit 5ede82b8ccb652382c106d53f656ed67997d76e8 from qemu
2018-03-07 08:10:01 -05:00
Richard Henderson d1da0b8f6d
tcg/aarch64: Add vector operations
Backports commit 14e4c1e2355473ccb2939afc69ac8f25de103b92 from qemu
2018-03-07 08:07:58 -05:00
Richard Henderson b3e89e9996
tcg/i386: Add vector operations
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.

The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and adjusts how all instructions should be
encoded.

Given the relatively narrow 2 year window between possible to support
and desirable to support, and to vastly simplify code maintainence,
I am only planning to support AVX1 and later cpus.

Backports commit 770c2fc7bb70804ae9869995fd02dadd6d7656ac from qemu
2018-03-07 08:07:40 -05:00
Richard Henderson 16a0a3e156
target/arm: Use vector infrastructure for aa64 orr/bic immediate
Backports commit 064e265d5680e5c605d6ee8370fc1e8da094e66d from qemu
2018-03-06 16:17:42 -05:00
Richard Henderson c5c8488928
target/arm: Use vector infrastructure for aa64 multiplies
Backports commit 0c7c55c492c918b6275baa3fee8b176c31465e3c from qemu
2018-03-06 16:14:47 -05:00
Richard Henderson 955fec9300
target/arm: Use vector infrastructure for aa64 compares
Backports commit 79d61de6bdc3980f0efef85f7539e129ab8a4a40 from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson 5626cb714e
target/arm: Use vector infrastructure for aa64 constant shifts
Backports commit cdb45a6063feb5efbb5896795e791dd3db006fbb from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson a63be5a7aa
target/arm: Use vector infrastructure for aa64 dup/movi
Backports commit 861a1ded24917843b9a5a99ea0a6b37c2c9a1930 from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson 84f848d876
target/arm: Use vector infrastructure for aa64 mov/not/neg
Backports commit 377ef731a85773788ae328e638698d27691bd77d from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson 03b76589b4
target/arm: Use vector infrastructure for aa64 add/sub/logic
Backports commit bc48092f5865c20893bb19200a7a320feac99eeb from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson f30abaea66
target/arm: Align vector registers
Backports commit 8b3495ea195503922c1e00253495cb6887b99dd5 from qemu
2018-03-06 16:10:10 -05:00
Richard Henderson 7f55d6ed69
tcg/optimize: Handle vector opcodes during optimize
Trivial move and constant propagation. Some identity and constant
function folding, but nothing that requires knowledge of the size
of the vector element.

Backports commit 170ba88f45bd7b1c5593021ed8e174f663b0bd1a from qemu
2018-03-06 16:10:09 -05:00
Richard Henderson ac4d051b05
tcg: Add generic vector helpers with a scalar operand
Use dup to convert a non-constant scalar to a third vector.

Add addition, multiplication, and logical operations with an immediate.
Add addition, subtraction, multiplication, and logical operations with
a non-constant scalar. Allow for the front-end to build operations in
which the scalar operand comes first.

Backports commit 22fc3527034678489ec554e82fd52f8a7f05418e from qemu
2018-03-06 16:10:09 -05:00
Richard Henderson 57bdf0faa2
tcg: Add generic helpers for saturating arithmetic
No vector ops as yet. SSE only has direct support for 8- and 16-bit
saturation; handling 32- and 64-bit saturation is much more expensive.

Backports commit f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd from qemu
2018-03-06 16:10:09 -05:00
Richard Henderson ab8579123e
tcg: Add generic vector ops for multiplication
Backports commit 3774030a3e523689df24a7ed22854ce7a06b0116 from qemu
2018-03-06 16:10:08 -05:00
Richard Henderson f9c4930ecd
tcg: Add generic vector ops for comparisons
Backports commit 212be173f01e85e6589fd76676827953a84a732b from qemu
2018-03-06 16:09:38 -05:00
Richard Henderson 577ee114c3
tcg: Add generic vector ops for constant shifts
Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends. Do
go ahead and provide them in case they are needed for backend expansion.

Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
2018-03-06 14:03:30 -05:00
Richard Henderson 64365612bf
tcg: Add generic vector expanders
Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
2018-03-06 13:42:52 -05:00
Richard Henderson 12fb906688
tcg: Standardize integral arguments to expanders
Some functions use intN_t arguments, some use uintN_t, some just
used "unsigned". To aid putting function pointers in tables, we
need consistency.

Backports commit 474b2e8f0f765515515b495e6872b5e18a660baf from qemu
2018-03-06 12:18:28 -05:00
Richard Henderson b9cd924fa5
tcg: Add types and basic operations for host vectors
Nothing uses or enables them yet.

Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
2018-03-06 12:13:32 -05:00
Richard Henderson 9ef32fc039
tcg: Allow multiple word entries into the constant pool
This will be required for storing vector constants.

Backports commit da73a4abca6acefc4bb55d30bd0242bdaddb6045 from qemu
2018-03-06 11:43:21 -05:00
Marc-André Lureau 001a86f02d
build-sys: add --enable-sanitizers
Typical slowdown introduced by AddressSanitizer is 2x.
UBSan shouldn't have much impact on runtime cost.

Enable it by default when --enable-debug, unless --disable-sanitizers.

Backports commit 247724cb302af5d70c8853154b640dfabf2bbb56 from qemu
2018-03-06 11:38:54 -05:00
Daniel P. Berrange a78892c2f5
configure: allow use of python 3
Backports commit c21965a0c8b979c306e927f158257e5b0fa3a1f9 from qemu
2018-03-06 11:33:58 -05:00
Daniel P. Berrange 42b238b45b
qapi: force a UTF-8 locale for running Python
Python2 did not validate locale correctness when reading input data, so
would happily read UTF-8 data in non-UTF-8 locales. Python3 is strict so
if you try to read UTF-8 data in the C locale, it will raise an error
for any UTF-8 bytes that aren't representable in 7-bit ascii encoding.
e.g.

UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 54: ordinal not in range(128)
Traceback (most recent call last):
File "/tmp/qemu-test/src/scripts/qapi-commands.py", line 317, in <module>
schema = QAPISchema(input_file)
File "/tmp/qemu-test/src/scripts/qapi.py", line 1468, in __init__
parser = QAPISchemaParser(open(fname, 'r'))
File "/tmp/qemu-test/src/scripts/qapi.py", line 301, in __init__
previously_included)
File "/tmp/qemu-test/src/scripts/qapi.py", line 348, in _include
exprs_include = QAPISchemaParser(fobj, previously_included, info)
File "/tmp/qemu-test/src/scripts/qapi.py", line 271, in __init__
self.src = fp.read()
File "/usr/lib64/python3.5/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]

More background on this can be seen in

https://www.python.org/dev/peps/pep-0538/

Many distros support a new C.UTF-8 locale that is like the C locale,
but with UTF-8 instead of 7-bit ASCII. That is not entirely portable
though. This patch thus sets the LANG to "C", but overrides LC_CTYPE
to be en_US.UTF-8 locale. This gets us pretty close to C.UTF-8, but
in a way that should be portable to everywhere QEMU builds.

This patch only forces UTF-8 for QAPI scripts, since that is the one
showing the immediate error under Python3 with C locale, but potentially
we ought to force this for all python scripts used in the build process.

Backports commit d4e5ec877ca698a87dabe68814c6f93668f50c60 from qemu
2018-03-06 11:32:48 -05:00
Daniel P. Berrange 4fb711df46
qapi: ensure stable sort ordering when checking QAPI entities
Some early python 3.x versions will have different default
ordering when calling the 'values()' method on a dict, compared
to python 2.x and later 3.x versions. Explicitly sort the items
to get a stable ordering.

Backports commit f7a5376d4b667cf6c83c1d640e32d22456d7b5ee from qemu
2018-03-06 11:30:31 -05:00
Daniel P. Berrange 74091c5976
qapi: Adapt to moved location of 'maketrans' function in py3
Backports commit 52c4272c6c916a53cde65b997e1a4e891c14dcef from qemu
2018-03-06 11:30:05 -05:00
Daniel P. Berrange 9e0335d129
qapi: adapt to moved location of StringIO module in py3
Backports commit 5f90af8e6b34f9e6b60eb05a15707a95a0febbde from qemu
2018-03-06 11:29:35 -05:00
Daniel P. Berrange 06f8bcbc97
qapi: Use OrderedDict from standard library if available
The OrderedDict class appeared in the 'collections' module
from python 2.7 onwards, so use that in preference to our
local backport if available.

Backports commit 38710a8994911d98acbe183a39ec3a53638de510 from qemu
2018-03-06 11:28:56 -05:00
Daniel P. Berrange a162292aae
qapi: use items()/values() intead of iteritems()/itervalues()
The iteritems()/itervalues() methods are gone in py3, but the
items()/values() methods are still around. The latter are less
efficient than the former in py2, but this has unmeasurably
small impact on QEMU build time, so taking portability over
efficiency is a net win.

Backports commit 2f8480447067d6f42af52a886385284ead052af9 from qemu
2018-03-06 11:28:22 -05:00
Daniel P. Berrange 57c29397c1
qapi: convert to use python print function instead of statement
Python 3 no longer supports the bare "print" statement, it must be
called as a normal function with round brackets. It is possible to
opt-in to this new syntax with Python 2.6 onwards by importing the
"print_function" from the "__future__" module, making it easy to
support Python 2 and 3 in parallel.

Backports commit ef9d9108917d6d5f903bca31602827e512a51c50 from qemu
2018-03-06 11:27:03 -05:00
Laurent Vivier db311b6802
target/m68k: add HMP command "info tlb"
Backports relevant parts of commit 2097dca6d3a30b80ac5a6232f518548d5ae644a9 from qemu
2018-03-06 11:23:10 -05:00
Laurent Vivier e1102bd396
target/m68k: add pflush/ptest
Backports commit e55886c3340c3a3f1267a3a3d42082008bb255fb from qemu
2018-03-06 11:21:51 -05:00
Laurent Vivier caee2d2dda
target/m68k: add moves
and introduce SFC and DFC control registers.

Backports commit 5fa9f1f28321f7268e68e58cff8c61a2ab817f91 from qemu
2018-03-06 11:17:36 -05:00
Laurent Vivier 8800971c07
target/m68k: add index parameter to gen_load()/gen_store() and Co.
The instruction "moves" can select source and destination
address space (user or kernel). This patch modifies
all the load/store functions to be able to provide
the address space the caller wants to use instead
of using the current one. All the callers are modified
to provide the default address space to these functions.

Backports commit 54e1e0b5b5ce4fc76335b1fbbf09cb8fdd5ab89d from qemu
2018-03-06 11:13:30 -05:00
Laurent Vivier 570a0e872f
target/m68k: add Transparent Translation
Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations

Backports commit c05c73b0838fc1b3fea87bc0ffa7b80b0556a2cb from qemu
2018-03-06 11:05:27 -05:00